9.3.1 Internal LDO

TPA3221 has a built in optional LDO (Low dropout voltage regulator) to supply the analog and digital circuits as well as the gate drive for the output stages. The LDO can be used in systems where only the high voltage power rail is available, hence no additional power supply rails need to be generated for the TPA3221 to operate. As being a linear regulator, the LDO will add to the power losses of the device due to the (PVDD-5V) voltage drop and the supply current for AVDD and GVDD given in the Electrical Characteristics table.

Figure 28. Internal LDO for Single Supply Systems

When using the internal LDO in TPA3221 the VDD terminal should be connected to a voltage source between 7V and PVDD. In a single supply system the VDD terminal should be connected directly to the PVDD terminal. The LDO output is connected to the AVDD terminal, and can be used to supply the gate drive by supplying the GVDD from AVDD through a RC filter for best noise performance as shown in Figure 28.

Figure 29. Internal LDO Bypass for Highest Power Efficiency

For highest system power efficiency the LDO can be bypassed by connecting VDD to an external 5 V supply. In this configuration AVDD and GVDD should be supplied by 5 V from the external power supply. GVDD should be supplied through a RC filter for best noise performance as shown in Figure 29.

9.3.1.1 Input Configuration, Gain Setting And Master / Slave Operation

TPA3221 is designed to accept either a differential or a single-ended audio input signal. To accept a wide range of system front ends TPA3221 has selectable input gain that allows full scale output with a wide range of input signal levels.

Best system noise performance is obtained with balanced audio interface. However, to be used in systems with only a single ended audio input signal available, one input terminal can be connected to AC ground, to accept single ended audio input signals.

Figure 30. Balanced Audio Input Configuration

In systems with single ended audio inputs the device gain will typically need to be set higher than for systems with balanced audio input signals.

Figure 31. Single Ended Audio Input Configuration

9.3.2 Gain Setting And Master / Slave Operation

The gain of TPA3221 is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets the GAIN in Master mode in gains of 18, 24, 30, 34 dB respectively, while the next four stages sets the GAIN in Slave mode in gains of 18, 24, 30, 34 dB respectively. The gain setting is latched when RESET goes high and cannot be changed while RESET is high. Table 2 shows the recommended resistor values, the state and gain:

Figure 32. Gain and Master / Slave Setup

For easy multi-channel system design TPA3221 has a Master / Slave feature that allows automatic synchronization of multiple slave devices operated at the PWM switching frequency of a master device. This benefits system noise performance by eliminating spurious crosstalk sum and difference tones due to unsynchronized channel-to-channel switching frequencies. Furthermore the Master / Slave scheme is designed to interleave switching of the individual channels in a multi-channel system such that the power supply current ripple frequency is moved to a higher frequency which reduces the RMS ripple current in the power supply bulk capacitors.

The Master / Slave scheme and the interleaving of the output stage switching is automatically configured by connecting the OSCx pins between a master and multiple slave devices. Connect the OSCx pins in either positive or negative polarity to configure either a Slave1 or Slave2 device. Connect the OSCM of the Master device to the OSCM of a slave device to configure for Slave1 or OSCP to configure for Slave2. Then connect the remaining OSCx pins between the master and slave devices. The Master, Slave1 and Slave2 PWM switching will be 30 degrees out of phase with each other. All switching channels are automatically synchronized by releasing /RESET on all devices at the same time.

Figure 33. Gain and Master PCB Implementation

Placement on the PCB and connection of multiple TPA3221 devices in a multi channel system is illustrated in Figure 33. Slave devices should be placed on either side of the master device, with a Slave1 device on one side of the Master device, and a Slave2 device on the other. In systems with more than 3 TPA3221 devices, the master should be in the middle, and every second slave devices should be a Slave1 or Slave 2 as illustrated in Figure 33. A 47kΩ pull up resistor to AVDD should be connected to the master device OSCM output and a 47kΩ pull down resistor to GND should be connected to the master OSCP CLK outputs.

9.3.3 AD-Mode and HEAD-Mode PWM Modulation

TPA3221 has the option of using either AD-Mode or HEAD-Mode PWM modulation scheme. AD mode has continuous switching of the two half bridge outputs in each BTL output channel. Both half bridge outputs are switching in HEAD mode, but with reduced duty cycle for idle operation and while playing small signals. With higher output levels one half bridge stops switching on HEAD mode operation. HEAD benefits both device power loss and EMI performance, where AD mode is considered to have the highest audio performance.

SPACE

Figure 34. AD-Mode Configuration

Figure 35. HEAD-Mode Configuration

Figure 36. AD Mode Output Waveforms, Idle

Figure 37. AD Mode Output Waveforms, High Level Output

Figure 38. AD Mode Speaker Output Signals, Low or and High Level Output

Figure 39. HEAD Mode Output Waveforms, Idle

Figure 40. HEAD Mode Output Waveforms, High Level Output

Figure 41. HEAD Mode Speaker Output Signals, Low Level Output

Figure 42. HEAD Mode Speaker Output Signals, High Level Output

9.3.4 Oscillator

The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.

To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency can be changed from nominal to higher values. These values should be chosen such that the nominal and the higher value switching frequencies together results in the fewest cases of interference throughout the AM band. The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in master mode according to the description in the Recommended Operating Conditions table.

For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to AVDD. This configures the OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter channel delay is automatically setup between the switching of the audio channels, which can be illustrated by no idle channels switching at the same time. This will not influence the audio output, but only the switch timing to minimize noise coupling between audio channels through the power supply to optimize audio performance and to get better operating conditions for the power supply. The inter channel delay will be setup for a slave device depending on the polarity of the OSC_I/O connection such that a slave mode 1 is selected by connecting the master device OSC_I/O to the slave 1 device OSC_I/O with same polarity (+ to + and - to -), and slave mode 2 is selected with the inverse polarity (+ to - and - to +).

9.3.5 Input Impedance

The TPA3221 input stage is a fully differential input stage and the input impedance changes with the gain setting from 7.7 kΩ at 34 dB gain to 47 kΩ at 18 dB gain. Table 1 lists the values from min to max gain. The tolerance of the input resistor value is ±20 % so the minimum value will be higher than 6.2 kΩ. The inputs need to be AC-coupled to minimize the output DC-offset and ensure correct ramping of the output voltages during power-ON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter with the following cut-off frequency:

If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. Table 3 lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10 times lower capacitors can used – for example, a 1 μF can be used.

The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum, film or ceramic. If a polarized type is used the positive connection should face such that the capacitor has a positive DC bias.

9.3.6 Error Reporting

The FAULT, and OTW_CLIP, pins are active-low, open-drain outputs. The FAULT function is for protection-mode signaling to a system-control device. Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, OTW_CLIP goes low when the device junction temperature exceeds 125°C (see Table 4).

Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI recommends monitoring the OTW_CLIP signal using the system microcontroller and responding to an overtemperature warning signal by turning down the volume to prevent further heating of the device resulting in device shutdown (OTE).

To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and OTW_CLIP outputs.

9.4.1 Powering Up

The TPA3221 does not require a power-up sequence because of the integrated undervoltage protection (UVP), but it is recommended to hold RESET low until PVDD supply voltage is stable to avoid audio artifacts. The outputs of the H-bridges remain in a high-impedance state until the gate-drive supply (GVDD) and AVDD voltages are above their UVP voltage thresholds (see the Electrical Characteristics table of this data sheet). This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pull-down of the half-bridge output as well as initiating a controlled ramp up sequence of the output voltage.

Figure 47. Startup Timing

When RESET is released to turn on TPA3221, FAULT signal will turn low and AVDD voltage regulator will be enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). After a pre-charge time to stabilize the DC voltage across the input AC coupling capacitors, the ramp up sequence starts and completes once the CMUTE node is charged to its final value.

9.4.2 Powering Down

The TPA3221 does not require a power-down sequence. The device remains fully operational as long as the VDD, AVDD and PVDD voltages are above their undervoltage protection (UVP) voltage thresholds (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks by initiating a controlled ramp down sequence of the output voltage. The ramp down sequence will complete once the CMUTE node is discharged.

9.4.3 Device Reset

Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down is complete. Output pull downs are active in both BTL mode and PBTL mode with RESET low.

In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the RESET input low enables weak pull-down of the half-bridge outputs.

Asserting RESET low removes any fault information to be signaled on the FAULT output, that is, FAULT is forced high. A rising-edge transition on RESET allows the device to resume operation after a fault. To ensure thermal reliability, the rising edge of RESET must occur no sooner than 4 ms after the falling edge of FAULT.

The TPA3221 will enter a low power state once the ramp down sequence is complete.

9.4.4 Device Soft Mute

Asserting CMUTE low initiates the device soft mute function. The soft mute function initiates a ramp down sequence of the outputs, and the output FETs go into a Hi-Z state after the ramp down is complete. All internal circuits are powered while in soft mute state. External control of the soft mute function must provide high impedance output when not engaged (open drain output) to allow the CMUTE node to charge/discharge during device ramp up and ramp down when de-asserting and asserting RESET.

9.4.5 Device Protection System

The TPA3221 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, overvoltage and undervoltage. The TPA3221 responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been removed, that is, the supply voltage has increased. The device will handle errors, as shown in Table 5.

Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching, does not assert FAULT).

9.4.5.1 Overload and Short Circuit Current Protection

TPA3221 has fast reacting current sensors on all high-side and low-side FETs. To prevent output current from increasing beyond the overcurrent threshold, TPA3221 uses current limiting of the output current for each switching cycle (Cycle By Cycle Current Control, CB3C) in case of excess output current. CB3C prevents premature shutdown due to high output current transients caused by high level music transients and a drop of real speaker’s load impedance, and allows the output current to be limited to a maximum programmed level. If the maximum output current persists, i.e. the power stage being overloaded with too low load impedance, the device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z) state until a RESET cycle is initiated. CB3C works individually for each full-bridge output. If an over current event is triggered, CB3C performs a state flip of the full-bridged output that is cleared upon beginning of next PWM frame.

Figure 48. CB3C Timing Example

9.4.5.2 Signal Clipping and Pulse Injector

A built in activity detector monitors the PWM activity of the OUT_X pins. TPA3221 is designed to drive unclipped output signals all the way to PVDD and GND rails. In case of audio signal clipping when applying excessive input signal voltage, or in case of CB3C current protection being active, the amplifier feedback loop of the audio channel will respond to this condition with a saturated state, and the output PWM signals will stop unless special circuitry is implemented to handle this situation. To prevent the output PWM signals from stopping in a clipping or CB3C situation, narrow pulses are injected to the gate drive to maintain output activity. The injected narrow pulses are injected at every 4^th PWM frame, and thus the effective switching frequency during this state is reduced to 1/4 of the normal switching frequency.

Signal clipping is signalled on the OTW_CLIP pin and is self clearing when signal level reduces and the device reverts to normal operation. The OTW_CLIP pulses starts at the onset to output clipping, typically at a THD level around 0.01%, resulting in narrow OTW_CLIP pulses starting with a pulse width of ~500ns.

Figure 49. Signal Clipping PWM and Speaker Output Signals