JAJSD69A February   2016  – October 2016 TPA3255

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Audio Characteristics (BTL)
    7. 7.7  Audio Characteristics (SE)
    8. 7.8  Audio Characteristics (PBTL)
    9. 7.9  Typical Characteristics, BTL Configuration
    10. 7.10 Typical Characteristics, SE Configuration
    11. 7.11 Typical Characteristics, PBTL Configuration
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Protection System
        1. 9.4.1.1 Overload and Short Circuit Current Protection
        2. 9.4.1.2 Signal Clipping and Pulse Injector
        3. 9.4.1.3 DC Speaker Protection
        4. 9.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 9.4.1.5 Overtemperature Protection OTW and OTE
        6. 9.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 9.4.1.7 Fault Handling
        8. 9.4.1.8 Device Reset
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 PCB Material Recommendation
          4. 10.2.1.2.4 Oscillator
      2. 10.2.2 Application Curves
      3. 10.2.3 Typical Application, Single Ended (1N) SE
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedures
        3. 10.2.3.3 Application Curves
      4. 10.2.4 Typical Application, Differential (2N) PBTL
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedures
        3. 10.2.4.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 VDD Supply
      2. 11.1.2 GVDD_X Supply
      3. 11.1.3 PVDD Supply
    2. 11.2 Powering Up
    3. 11.3 Powering Down
    4. 11.4 Thermal Design
      1. 11.4.1 Thermal Performance
      2. 11.4.2 Thermal Performance with Continuous Output Power
      3. 11.4.3 Thermal Performance with Non-Continuous Output Power
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
      1. 12.2.1 BTL Application Printed Circuit Board Layout Example
      2. 12.2.2 SE Application Printed Circuit Board Layout Example
      3. 12.2.3 PBTL Application Printed Circuit Board Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

The TPA3255 is available in a thermally enhanced TSSOP package.

The package type contains a PowerPAD™ that is located on the top side of the device for convenient thermal coupling to the heat sink.

DDV Package
HTSSOP 44-Pin
(Top View)

Pin Functions

NAME NO. I/O DESCRIPTION
AVDD 14 P Internal voltage regulator, analog section
BST_A 44 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
BST_B 43 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
BST_C 24 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
BST_D 23 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
CLIP_OTW 21 O Clipping warning and Over-temperature warning; open drain; active low. Do not connect if not used.
C_START 15 O Startup ramp, requires a charging capacitor to GND
DVDD 11 P Internal voltage regulator, digital section
FAULT 19 O Shutdown signal, open drain; active low. Do not connect if not used.
FREQ_ADJ 8 O Oscillator freqency programming pin
GND 12, 13, 25, 26, 33, 34, 41, 42 P Ground
GVDD_AB 1 P Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
GVDD_CD 22 P Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
INPUT_A 5 I Input signal for half bridge A
INPUT_B 6 I Input signal for half bridge B
INPUT_C 16 I Input signal for half bridge C
INPUT_D 17 I Input signal for half bridge D
M1 3 I Mode selection 1 (LSB)
M2 4 I Mode selection 2 (MSB)
OC_ADJ 7 I/O Over-Current threshold programming pin
OSC_IOM 9 I/O Oscillator synchronization interface. Do not connect if not used.
OSC_IOP 10 O Oscillator synchronization interface. Do not connect if not used.
OUT_A 39, 40 O Output, half bridge A
OUT_B 35 O Output, half bridge B
OUT_C 32 O Output, half bridge C
OUT_D 27, 28 O Output, half bridge D
PVDD_AB 36, 37, 38 P PVDD supply for half-bridge A and B
PVDD_CD 29, 30, 31 P PVDD supply for half-bridge C and D
RESET 18 I Device reset Input; active low
VDD 2 P Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
VBG 20 P Internal voltage reference requires a 1-µF capacitor to GND for decoupling.
PowerPad™ P Ground, connect to grounded heat sink

Table 1. Mode Selection Pins

MODE PINS(2) INPUT MODE(1) OUTPUT CONFIGURATION DESCRIPTION
M2 M1
0 0 2N + 1 2 × BTL Stereo BTL output configuration
0 1 2N/1N + 1 1 x BTL + 2 x SE 2.1 BTL + SE mode. Channel AB: BTL, channel C + D: SE
1 0 2N + 1 INPUT_C INPUT_D
1 x PBTL Parallelled BTL configuration. Connect INPUT_C and INPUT_D to GND.(2) 0 0
1 x BTL Mono BTL configuration. BTL channel AB active, channel CD not switching. Connect INPUT_C to DVDD and INPUT_D to GND.(2) 1 0
1 1 1N +1 4 x SE Single ended output configuration
(1) 2N refers to differential input signal, 1N refers to single ended input signal. +1 refers to number of logic control (RESET) input pins.
(2) 1 refers to logic high (DVDD level), 0 refers to logic low (GND).