9.4.7 PGb, FLTb, and Timer Operations

The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across internal FET. PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor C_OUT is still charging. PGb goes active-low about 3.4 ms after C_OUT is charged. This delay allows the internal FET to fully turnon and any transients in the power circuits to end before the converter starts up. This type of sequencing prevents the downstream converter from demanding full current before the power-limiting engine allows the internal FET to conduct the full current set by the current limit I_LIM. Failure to observe this precaution may prevent the system from starting. The pullup resistor shown on the PGb pin in the typical system block diagram application diagram Figure 41 is illustrative only; the actual connection to the converter depends on the application. The PGb pin may indicate that inrush has ended before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its full operating voltage. After the hot-swap circuit successfully starts up, the PGb pin can return to a high-impedance status whenever the drain-to-source voltage of internal FET exceeds its upper threshold of 340 mV, which presents the downstream converters a warning flag. This flag may occur as a result of overload fault, output short fault, input overvoltage, higher die temperature, or the GATE shutdown by UVLO, EN.

FLTb is an indicator that the allowed fault-timer period during which the load current can exceed the programmed current limit (but not the fast-trip threshold) expires. The fault timer starts when a current of approximately 10 μA begins to flow into the external capacitor C_T, and ends when the voltage of C_T reaches TIMER upper threshold, that is, 1.35 V. FLTb pulls low at the end of the fault timer. Otherwise, FLTb assumes a high-impedance state.

The fault-timer state requires an external capacitor C_T connected between the TIMER pin and GND pin. The duration of the fault timer is the charging time of C_T from 0 V to its upper threshold of 1.35 V. The fault timer begins to count under any of the following three conditions:

1. In the inrush mode, TIMER begins to source current to the timer capacitor, C_T, when device is enabled. TIMER begins to sink current from the timer capacitor, C_T when V_{(GATE – VCC)} exceeds the timer activation voltage (see the Inrush Operation section). If V_{(GATE – VCC)} does not reach the timer activation voltage before TIMER reaches 1.35 V, then the TPS2475x disables the internal FET. After the MOSFET turns off, the timer goes into either latch mode (TPS24750) or retry mode (TPS24751).
2. In an overload fault, TIMER begins to source current to the timer capacitor, C_T, when the load current exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, C_T, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24750) or retry mode (TPS24751).
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, C_T, when the load current exceeds the programmed current limits following a fast-trip shutdown of internal FET. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, C_T, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24750) or retry mode (TPS24751).

If the fault current drops below the programmed current limit within the fault timer period, V_TIMER decreases and the internal pass MOSFET remains enabled.

The behaviors of TIMER are different in the latch mode and retry mode. If the timer capacitor reaches the upper threshold of 1.35 V, then:

• In latch mode(TPS24750), the TIMER pin continues to charge and discharge the attached capacitor periodically until device is disabled by UVLO, EN, or OV, as shown in Figure 38.
• In retry mode(TPS24751), TIMER charges and discharges C_T between the lower threshold of 0.35 V and the upper threshold of 1.35 V for sixteen cycles before the device attempts to re-start. The TIMER pin is pulled to GND at the end of the 16^th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is removed or the TPS2475x is disabled by UVLO, EN or OV.