JAJSGL9C October   2013  – December 2018 TPS24750 , TPS24751

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション回路図 (12V、10A)
      2.      過渡出力短絡応答
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Descriptions
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  DRAIN
      2. 9.3.2  EN
      3. 9.3.3  FLTb
      4. 9.3.4  GATE
      5. 9.3.5  GND
      6. 9.3.6  IMON
      7. 9.3.7  OUT
      8. 9.3.8  OV
      9. 9.3.9  PGb
      10. 9.3.10 PROG
      11. 9.3.11 SENSE
      12. 9.3.12 TIMER
      13. 9.3.13 VCC
    4. 9.4 Device Functional Modes
      1. 9.4.1 Board Plug-In
      2. 9.4.2 Inrush Operation
      3. 9.4.3 Action of the Constant-Power Engine
      4. 9.4.4 Circuit Breaker and Fast Trip
      5. 9.4.5 Automatic Restart
      6. 9.4.6 Start-Up with Short on Output
      7. 9.4.7 PGb, FLTb, and Timer Operations
        1. 9.4.7.1 Overtemperature Shutdown
        2. 9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power-Limited Start-Up
          1. 10.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
          2. 10.2.2.1.2 STEP 2. Choose Power-Limit Value, PLIM, and RPROG
          3. 10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
          4. 10.2.2.1.4 STEP 4. Calculate the Retry-Mode Duty Ratio
          5. 10.2.2.1.5 STEP 5. Select R1, R2, and R3 for UV and OV
          6. 10.2.2.1.6 STEP 6. Choose R4, R5, and C1
        2. 10.2.2.2 Alternative Design Example: Gate Capacitor (dv/dt) Control in Inrush Mode
        3. 10.2.2.3 Additional Design Considerations
          1. 10.2.2.3.1 Use of PGb
          2. 10.2.2.3.2 Output Clamp Diode
          3. 10.2.2.3.3 Gate Clamp Diode
          4. 10.2.2.3.4 Bypass Capacitors
          5. 10.2.2.3.5 Output Short-Circuit Measurements
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 Transient Thermal Impedance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Export Control Notice
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.2.1.2 STEP 2. Choose Power-Limit Value, PLIM, and RPROG

The internal MOSFET dissipates large amounts of power during inrush. The power limit PLIM of the TPS2475x must be set to prevent the internal FET die temperature from exceeding a short-term maximum temperature, TJ(MAX)2. The short-term TJ(MAX)2 could be set ≤125°C to have sufficient margin to the internal maximum FET junction temperature. Equation 6 is an expression for calculating PLIM.

Equation 6. TPS24750 TPS24751 EQ_Plim_3_slvsc87.gif

In the above equation, RθCA= RθJA – RθJC

Where, RθCA is the case-to-ambient thermal resistance (RθCA is a strong function of the user defined PCB layout and heat sinking provided on Pad-2 of the device and can vary accordingly), RθJA is the junction-to-ambient thermal resistance and RθJC is the junction-to-case thermal resistance of the device, (In Equation 6 , the values are used from the TPS2475x Thermal Information table), rDS(on) is internal FET on-resistance at the maximum operating temperature, and the factor of 0.8 represents the tolerance of the constant-power engine. For an ambient temperature of 60°C, the calculated maximum PLIM is 33 W. Power limit selected must be lower than value obtained in Equation 6, to have substantial safe margin considering the tolerance of components and extended system temperatures. Power limit (PLIM) of 21 W is considered for this design. From Equation 1, a 64.9-kΩ, 1% resistor is selected for RPROG (see Equation 7).

Equation 7. TPS24750 TPS24751 EQ_Rprog_slvsc87.gif

Power Limit fold back (PLIM-FB) is the ratio of operating current (ILIM) and minimum power limited (regulated) current (when VOUT = 0V). Degradation of programmed power limit (PLIM) accuracy and start up issues may occur if PLIM-FB is too large. Equation 8 calculates VSNS-PL_MIN (minimum sense voltage during power limit) and PLIM-FB. To ensure reliable operation, verify that PLIM-FB < 12 and VSNS-PL_MIN ≥ 3mV.

Equation 8. TPS24750 TPS24751 EQ_Vsns_LVSC87.gif

If the above conditions are not met, please adjust and align RSENSE, PLIM set, and TA(MAX) appropriately to satisfy the above conditions.