JAJSGL5C December   2018  – August 2019 TPS3840

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
      2.      TPS3840 の標準的な消費電流
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage (VDD)
        1. 9.3.1.1 VDD Hysteresis
        2. 9.3.1.2 VDD Transient Immunity
      2. 9.3.2 User-Programmable Reset Time Delay
      3. 9.3.3 Manual Reset (MR) Input
      4. 9.3.4 Output Logic
        1. 9.3.4.1 RESET Output, Active-Low
        2. 9.3.4.2 RESET Output, Active-High
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operation (VDD > VDD(min))
      2. 9.4.2 VDD Between VPOR and VDD(min)
      3. 9.4.3 Below Power-On-Reset (VDD < VPOR)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Design 2: Battery Voltage and Temperature Monitor
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
      4. 10.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
      5. 10.2.5 Application Curve: TPS3840EVM
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイスの項目表記
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

At 1.5 V ≤ VDD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C. 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage 1.5 10 V
VIT- Negative-going input threshold accuracy(1) -40°C to 125°C –1.5 1 1.5 %
VHYS Hysteresis on VIT- pin VIT- = 3.1 V to 4.9 V 175 200 225 mV
VHYS Hysteresis on VIT- pin VIT- = 1.6 V to 3.0 V 75 100 125 mV
IDD Supply current into VDD pin VDD = 1.5 V  < VDD < 10 V
VDD > VIT+(3)
TA = -40°C to 125°C		 300 700 nA
VMR_L Manual reset logic low input(2) 600 mV
VMR_H Manual reset logic high input(2) 0.7VDD V
RMR Manual reset internal pull-up resistance 100 kΩ
RCT CT pin internal resistance 350 500 650 kΩ
TPS3840PL (Push-Pull Active-Low)
VPOR Power on Reset Voltage(4) VOL(max) = 200 mV
IOUT(Sink) = 200 nA		 300 mV
VOL Low level output voltage
 		 1.5 V < VDD < 5 V
VDD < VIT-
IOUT(Sink) = 2 mA		 200 mV
VOH High level output voltage
 		 1.5 V < VDD < 5 V
VDD > VIT+(3)
IOUT(Source) = 2 mA		 0.8VDD V
5 V < VDD < 10 V
VDD > VIT+(3)
IOUT(Source) = 5 mA		 0.8VDD V
TPS3840PH (Push-Pull Active-High)
VPOR Power on Reset Voltage(4) VOH, IOUT(Source) = 500 nA 950 mV
VOL Low level output voltage
 		 1.5 V < VDD < 5 V
VDD > VIT+(3)
IOUT(Sink) = 2 mA		 200 mV
1.5 V < VDD < 5 V
VDD > VIT+(3)
IOUT(Sink) = 5 mA		 200 mV
VOH High level output voltage
 		 1.5 V < VDD < 5 V, VDD < VIT-,
IOUT(Source) = 2 mA		 0.8VDD V
TPS3840DL(Open-Drain)
VPOR Power on Reset Voltage(4) VOL(max) = 0.2 V
IOUT (Sink) = 5.6 uA		 950 mV
VOL Low level output voltage
 		 1.5 V < VDD < 5 V
VDD < VIT-
IOUT(Sink) = 2 mA		 200 mV
Ilkg(OD) Open-Drain output leakage current RESET pin in High Impedance,
VDD = VRESET = 5.5 V
VIT+ < VDD 		90 nA
(1) VIT- threshold voltage range from 1.6 V to 4.9 V in 100 mV steps, for released versions see Device Voltage Thresholds table.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR
(3) VIT+ = VHYS + VIT-
(4) VPOR is the minimum VDD voltage level for a controlled output state. VDD slew rate  ≤ 100mV/µs