7.3.1 Output Noise

A precision band-gap reference is used to generate the internal reference voltage, V_REF. This reference is the dominant noise source within the TPS732 and it generates approximately 32 µV_RMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by:

Equation 1.

Because the value of V_REF is 1.2 V, this relationship reduces to:

Equation 2.

An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, C_NR, is connected from NR to ground. For C_NR = 10 nF, the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the approximate relationship:

Equation 3.

for C_NR = 10 nF.

This noise reduction effect is shown as RMS Noise Voltage vs C_NR (Figure 18) in the Typical Characteristics section.

The TPS73201 adjustable version does not have the NR pin available. However, connecting a feedback capacitor, C_FB, from the output to the feedback pin (FB) reduces output noise and improve load transient performance.

The TPS732 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above V_OUT. The charge pump generates approximately 250 μV of switching noise at approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of I_OUT and C_OUT.

7.3.2 Internal Current Limit

The TPS732 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when V_OUT drops below 0.5 V. See Figure 10 in the Typical Characteristics section for a graph of I_OUT vs V_OUT.

Note from Figure 10 that approximately –0.2 V of V_OUT results in a current limit of 0 mA. Therefore, if OUT is forced below –0.2 V before EN goes high, the device may not start up. In applications that work with both a positive and negative voltage supply, the TPS732 should be enabled first.

7.3.3 Enable Pin and Shutdown

The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A V_EN below 0.5 V (maximum) turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shut down the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated V_OUT (see Figure 21).

When shutdown capability is not required, EN can be connected to V_IN. However, the pass gate may not be discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after V_IN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power up. In addition, for V_IN ramp times slower than a few milliseconds, the output may overshoot upon power up.

Note that current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit section.

7.3.4 Dropout Voltage

The TPS732 uses an NMOS pass transistor to achieve extremely low dropout. When (V_IN – V_OUT) is less than the dropout voltage (V_DO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the R_DS(on) of the NMOS pass element.

For large step changes in load current, the TPS732 requires a larger voltage drop from V_IN to V_OUT to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the DC dropout. Values of (V_IN – V_OUT) above this line ensure normal transient response.

Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (V_IN to V_OUT voltage drop). Under worst-case conditions [full-scale instantaneous load change with (V_IN – V_OUT) close to DC dropout levels], the TPS732 can take a couple of hundred microseconds to return to the specified regulation accuracy.

7.3.5 Reverse Current

The NMOS pass element of the TPS732 provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate.

After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. Additional current will flow into the OUT pin due to the 80-kΩ internal resistor divider to ground (see Figure 29 and Figure 30).

For the TPS73201, reverse current may flow when V_FB is more than 1 V above V_IN.

7.4.1 Normal Operation With 1.7 V ≤ V_IN ≤ 5.5 V and V_EN ≥ 1.7 V

The TPS732 family requires an input voltage of at least 1.7 V to function properly and attempt to maintain regulation.

When operating the device near 5.5 V, take care to suppress any transient spikes that may exceed the 6-V absolute maximum voltage rating. The device should never operate at a DC voltage greater than 5.5 V.