SBVS343 March 2019 TPS7A78
ADVANCE INFORMATION for pre-production products; subject to change without notice.
The power-good circuit monitors the voltage at the LDO_OUT pin to indicate the status of the output voltage VLDO_OUT. When VLDO_OUT falls below the PG pin typical percentage value of VLDO_OUT as specified in the Typical Characteristics section, the PG pin open-drain logic engages and pulls the PG pin close to GND. When the VLDO_OUT voltage exceeds the PG pin trip value as specified in the Typical Characteristics section, the PG pin becomes high impedance.
By pulling up the PG pin to the LDO_IN pin by a pullup resistor, a downstream device such as a MCU can receive the power-good logic signal to wake-up and resume normal operation.
An external DC rail can also be used to pullup the PG pin signal via a pullup resistor only when the external DC rail shares the same reference GND with the device GND.
Use the recommended pullup resistor value specified in the Electrical Characterstics table for the PG pin.