SBVS343 March   2019 TPS7A78

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. Features
  2. Applications
    1.     Typical Schematic
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Active Bridge Control
      2. 7.3.2 Full Bridge (FB) and Half Bridge Configurations
      3. 7.3.3 4 to 1 Switch Capacitor Voltage Reduction
      4. 7.3.4 VLDO_IN Overvoltage Protection
      5. 7.3.5 Dropout Voltage Regulation
      6. 7.3.6 Current Limit
      7. 7.3.7 Programmable Power-Fail Detection
      8. 7.3.8 Power-Good (PG) Detection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation: AC Input mode
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disabled Mode
      4. 7.4.4 Normal Operation: DC Input mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Cap-Drop Capacitor CS
      3. 8.1.3 Surge Resistor RS
      4. 8.1.4 Input and Output Capacitors Requirements
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
発注情報

Power-Good (PG) Detection

The power-good circuit monitors the voltage at the LDO_OUT pin to indicate the status of the output voltage VLDO_OUT. When VLDO_OUT falls below the PG pin typical percentage value of VLDO_OUT as specified in the Typical Characteristics section, the PG pin open-drain logic engages and pulls the PG pin close to GND. When the VLDO_OUT voltage exceeds the PG pin trip value as specified in the Typical Characteristics section, the PG pin becomes high impedance.

By pulling up the PG pin to the LDO_IN pin by a pullup resistor, a downstream device such as a MCU can receive the power-good logic signal to wake-up and resume normal operation.

NOTE

An external DC rail can also be used to pullup the PG pin signal via a pullup resistor only when the external DC rail shares the same reference GND with the device GND.

Use the recommended pullup resistor value specified in the Electrical Characterstics table for the PG pin.