SBVS343 March   2019 TPS7A78

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. Features
  2. Applications
    1.     Typical Schematic
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Active Bridge Control
      2. 7.3.2 Full Bridge (FB) and Half Bridge Configurations
      3. 7.3.3 4 to 1 Switch Capacitor Voltage Reduction
      4. 7.3.4 VLDO_IN Overvoltage Protection
      5. 7.3.5 Dropout Voltage Regulation
      6. 7.3.6 Current Limit
      7. 7.3.7 Programmable Power-Fail Detection
      8. 7.3.8 Power-Good (PG) Detection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation: AC Input mode
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disabled Mode
      4. 7.4.4 Normal Operation: DC Input mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Cap-Drop Capacitor CS
      3. 8.1.3 Surge Resistor RS
      4. 8.1.4 Input and Output Capacitors Requirements
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



Programmable Power-Fail Detection

The device monitors the AC supply voltage failure by monitoring the rectified voltage at CSCIN capacitor and pulls down the open-drain power-fail (PF) pin close to GND. The device detects AC supply failure through the resistor divider voltage off VSCIN input to Power Fail Detect ( PFD) analog input pin. When AC supply falls below the Power Fail Detection (PFD) programmed threshold specified in the Typical Characteristics section, then PFD comparator trips causing PF to be pulled close to GND.

By pulling-up PF pin to VLDO_IN by a pullup resistor, an MCU can monitor PF signal and use this early warning to shift to a backup power solution and perform a controlled shutdown to prevent loss of data.

to switch to a battery supply or safely powers down the meter. Pulling-up PF pin to LDO_IN voltage rather than LDO_OUT voltage ensures the continuos monitoring of PF signal when LDO_OUT voltage is down due to a heavy load or short circuit event.


An external DC rail can also be used to pullup the PF pin signal via a pullup resistor only when the external DC rail shares the same reference GND with the device GND.

The resistors R1 and R2 in the Typical Schematic can be used to program the minimum AC supply voltage at which PF trips, use Equation 1 to calculate VSCIN (min) voltage resulting from the min AC supply voltage. Equation 1 uses 2.5 V droop as the typical recommended value for VSCIN (min) , however the designer can choose a different value based of design requirements.

Equation 1. VSCIN (min) = 4 ×(VLDO_OUT + 0.6 V) – 2.5 V

Use Equation 2 to calculate the values of R1 and R2 resistors.

Equation 2. PFD = VSCIN (min) × ( R2 ÷ (R1+ R2))

To minimize the resistor divider current loss from the bulk capacitor CSCIN, set the R1 value to be as close to the maximum value specified in the Recommended Operating Conditions table, then calculate R2. Use the recommended pullup resistor value in the Electrical Characterstics table for the PF pin.