11.1.1 Board Layout Recommendations To Improve PSRR And Noise Performance

To improve AC performance such as PSRR, output noise, and transient response, designing with separate ground planes for V_I and V_O, with each ground plane connected only at the GND pin of the device, is recommended. In addition, the ground connection for the noise-reduction capacitor should connect directly to the GND pin of the device.

High ESR capacitors may degrade PSRR.

11.3.1 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of overheating.

Any activation of the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C (maximum). To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS7A8101-Q1 device has been designed to protect against overload conditions. The internal thermal protection circuitry was not intended to replace proper heatsinking. Continuously running the TPS7A8101-Q1 device into thermal shutdown degrades device reliability.

11.3.2 Package Mounting

See the Mechanical, Packaging, and Orderable Information section for solder pad footprint recommendations and recommended land patterns.

11.3.3 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.

The power dissipation of the device depends on input voltage and load conditions. To calculate the device power dissipation, use Equation 3.

Using the lowest possible input voltage necessary to achieve the required output voltage regulation minimizes power dissipation and achieves greater efficiency.

On the SON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or can be left floating; however, the pad should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device. Calculate the maximum junction-to-ambient thermal resistance using Equation 4.

Equation 4.

Once the maximum R_θJA value is calculated, use Figure 45 to estimate the minimum amount of PCB copper area needed for appropriate heatsinking.

The R_θJA value at board size of 9 in² (that is, 3 in × 3 in) is a JEDEC standard.

Figure 45. R_θJA vs Board Size

Figure 45 shows the variation of R_θJA as a function of ground plane copper area in the board. Figure 45 is intended as a guideline only to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments.

11.3.4 Estimating Junction Temperature

Using the thermal metrics Ψ_JT and Ψ_JB, as shown in the Thermal Information table, the junction temperature can be estimated with the corresponding equations, Equation 5 and Equation 6. For backwards compatibility, an older θ_JC,Top parameter is listed as well.

Figure 46. Measuring Points for T_T and T_B

For more information about measuring T_T and T_B, see TI's application report SBVA025, Using New Thermal Metrics.

As shown in Figure 47, the new thermal metrics (Ψ_JT and Ψ_JB) have very little dependency on board size. That is, using Ψ_JT or Ψ_JB with Equation 5 is a good way to estimate T_J by simply measuring T_T or T_B, regardless of the application board size.

Figure 47. Ψ_JT and Ψ_JB vs Board Size

For a more detailed discussion of why TI does not recommend using R_θJC(top) to determine thermal characteristics, refer to TI's application report SBVA025, Using New Thermal Metrics. For further information, refer to TI's application report SPRA953, IC Package Thermal Metrics.