JAJSCR3A December   2016  – July 2017 TPSM84A21

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Package Specifications
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage (VADJ)
      2. 7.3.2  Input and Output Capacitance
      3. 7.3.3  Transient Response
        1. 7.3.3.1 Transient Response Waveforms
      4. 7.3.4  Oscillator Frequency
      5. 7.3.5  External Clock Syncronization
      6. 7.3.6  Soft Start
      7. 7.3.7  Power Good (PGOOD)
      8. 7.3.8  Gate Driver (VG)
      9. 7.3.9  Startup into Pre-biased Outputs
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Output Undervoltage/Overvoltage Protection
      13. 7.3.13 Enable (EN)
      14. 7.3.14 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Shutdown Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Input and Output Capacitance
        3. 8.2.2.3 Power Good (PGOOD)
        4. 8.2.2.4 External VG Voltage
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 EMI
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout

Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 20 and Figure 22 show typical, top-side PCB layouts. Some considerations for an optimized layout are:

  • Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
  • When adding input and output ceramic capacitors, place them close to the device pins to minimize high frequency noise.
  • Locate any additional output capacitors between the ceramic capacitors and the load.
  • Keep AGND and PGND separate from one another. The connection is made internal to the device.
  • Place RSET as close as possible to the VADJ pin.
  • Use multiple vias to connect the power planes to internal layers.

Layout Examples

The layout shown in Figure 20 shows the minimum solution size with only a single voltage setting resistor (R1) as the only additional required component. Figure 21 shows a typical internal PCB layer with a trace connecting the VS+ pin to VOUT near the load.

TPSM84A21 ToplayerMin2.gif Figure 20. Minimum Component Layout
TPSM84A21 Innerlayer.gif Figure 21. VS+ Trace on Internal Layer

Figure 22 shows a layout with the placement of additional ceramic input capacitors (C1, C3) and ceramic output capacitors (C2, C4) for designs that require additional ripple reduction or improved transient response. Figure 23 shows a typical internal PCB layer with a trace connecting the VS+ pin to VOUT near the load

TPSM84A21 Toplayer2.gif Figure 22. Layout with Optional CIN and COUT
TPSM84A21 Innerlayer2.gif Figure 23. VS+ Trace on Internal Layer

EMI

The TPSM84A21 is compliant with EN55022 Class B radiated emissions. Figure 24 to Figure 27 show typical examples of radiated emissions plots for the TPSM84A21. Graphs included show plots of the antenna in the horizontal and vertical positions.

TPSM84A21 A21EMI08Horiz2.gif
Figure 24. Radiated Emissions 12-V Input, 0.8-V Output,
10-A Load, Horizontal Antenna
TPSM84A21 A21EMI12Horiz2.gif Figure 26. Radiated Emissions 12-V Input, 1.2-V Output,
10-A Load, Horizontal Antenna
TPSM84A21 A21EMI08Vert3.gif
Figure 25. Radiated Emissions 12-V Input, 0.8-V Output,
10-A Load, Vertical Antenna
TPSM84A21 A21EMI12Vert2.gif Figure 27. Radiated Emissions 12-V Input, 1.2-V Output,
10-A Load, Vertical Antenna