JAJSDH9D August   2017  – May 2019 TUSB1042I

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      TUSB1042Iのアイ・ダイアグラム
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  DCI Specific Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 USB3.1 Modes
      5. 8.4.5 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 9. General Registers
      2. 8.6.2 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 10. USB3.1 Control/Status Registers (0x20)
      3. 8.6.3 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 11. USB3.1 Control/Status Registers (0x21)
      4. 8.6.4 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000100]
        1. Table 12. USB3.1 Control/Status Registers (0x22)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 AC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
USB Gen 2 Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
V(RX-DIFF-PP) Input differential peak-peak voltage swing linear dynamic range AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel 2000 mVpp
V(RX-DC-CM) Common-mode voltage bias in the receiver (DC) 0 V
R(RX-DIFF-DC) Differential input impedance (DC) Present after a GEN2 device is detected on TXP/TXN 72 120 Ω
R(RX-CM-DC) Receiver DC common mode impedance Present after a GEN2 device is detected on TXP/TXN 18 30 Ω
Z(RX-HIGH-IMP-DC-POS) Common-mode input impedance with termination disabled (DC) Present when no GEN2 device is detected on TXP/TXN. Measured over the range of 0-500mV with respect to GND. 25 kΩ
V(SIGNAL-DET-DIFF-PP) Input differential peak-to-peak signal detect assert level At 10 Gbps, no input loss, PRBS7 pattern 80 mV
V(RX-IDLE-DET-DIFF-PP) Input differential peak-to-peak signal detect de-assert Level At 10 Gbps, no input loss, PRBS7 pattern 60 mV
V(RX-LFPS-DET-DIFF-PP) Low frequency periodic signaling (LFPS) detect threshold Below the minimum is squelched 100 300 mV
V(RX-CM-AC-P) Peak RX AC common-mode voltage Measured at package pin 150 mV
C(RX) RX input capacitance to GND At 5 GHz 0.5 1 pF
RL(RX-DIFF) Differential return Loss 50 MHz – 1.25 GHz at 90 Ω –19 dB
5 GHz at 90 Ω –10 dB
RL(RX-CM) Common-mode return loss 50 MHz – 5 GHz at 90 Ω –10 dB
EQ(SS_TX) Receiver equalization for upstream facing port SSEQ[1:0] at 5 GHz 11 dB
EQ(SS_RX) Receiver equalization for downstream facing ports EQ[1:0] at 5 GHz 9 dB
USB Gen 2 Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX(DIFF-PP) Transmitter dynamic differential voltage swing range. 1600 mVPP
VTX(RCV-DETECT) Amount of voltage change allowed during receiver detection 600 mV
VTX(CM-IDLE-DELTA) Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS –600 600 mV
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC) 1.75 V
VTX(CM-AC-PP-ACTIVE) Tx AC common-mode voltage active Max mismatch from Txp + Txn for both time and amplitude 100 mVPP
VTX(IDLE-DIFF-AC-PP) AC electrical idle differential peak-to-peak output voltage At package pins 0 10 mV
VTX(IDLE-DIFF-DC) DC electrical idle differential output voltage At package pins after low pass filter to remove AC component 0 14 mV
VTX(CM-DC-ACTIVE-IDLE-DELTA) Absolute DC common-mode voltage between U1 and U0 At package pin 200 mV
RTX(DIFF) Differential impedance of the driver 75 120 Ω
CAC(COUPLING) AC coupling capacitor 75 265 nF
RTX(CM) Common-mode impedance of the driver Measured with respect to AC ground over
0–500 mV		 18 30 Ω
ITX(SHORT) TX short circuit current TX± shorted to GND 67 mA
CTX(PARASITIC) TX input capacitance for return loss At package pins, at 5 GHz 1.25 pF
RLTX(DIFF) Differential return loss 50 MHz – 1.25 GHz at 90 Ω -15 dB
5 GHz at 90 Ω -13 dB
RLTX(CM) Common-mode return loss 50 MHz – 5 GHz at 90 Ω -13 dB
AC Characteristics
Crosstalk Differential crosstalk between TX and RX signal pairs at 5 GHz –30 dB
C(P1dB-LF) Low frequency 1-dB compression point at 100 MHz, 200 mVPP < VID
< 2000 mVPP 		1300 mVPP
C(P1dB-HF) High frequency 1-dB compression point at 5 GHz, 200 mVPP < VID
< 2000 mVPP 		1000 mVPP
fLF Low frequency cutoff 200 mVPP< VID < 2000 mVPP 20 50 kHz
TX output deterministic jitter 200 mVPP < VID < 2000 mVPP, PRBS7, 10 Gbps 0.11 UIpp
200 mVPP < VID < 2000 mVPP, PRBS7, 5 Gbps 0.05 UIpp
TX output total jitter 200 mVPP < VID < 2000 mVPP, PRBS7, 10 Gbps 0.15 UIpp
200 mVPP < VID < 2000 mVPP, PRBS7, 5 Gbps 0.08 UIpp