JAJSGJ8C November   2018  – September 2019 UCC20225-Q1 , UCC20225A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Thermal Derating Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Propagation Delay and Pulse Width Distortion
    2. 8.2 Rising and Falling Time
    3. 8.3 PWM Input and Disable Response Time
    4. 8.4 Programable Dead Time
    5. 8.5 Power-up UVLO Delay to OUTPUT
    6. 8.6 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in UCC20225-Q1 family
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 Tying the DT Pin to VCC
        2. 9.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing PWM Input Filter
        2. 10.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 10.2.2.3 Gate Driver Output Resistor
        4. 10.2.2.4 Estimate Gate Driver Power Loss
        5. 10.2.2.5 Estimating Junction Temperature
        6. 10.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.6.1 Selecting a VCCI Capacitor
          2. 10.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.6.3 Select a VDDB Capacitor
        7. 10.2.2.7 Dead Time Setting Guidelines
        8. 10.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 認定
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC20225 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected outputs low, regardless of the status of the input pin (PWM).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (illustrated in Figure 33 ). In this condition, the upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device, typically around 1.5V, when no bias power is available. The clamp sinking current is limited only by the per-channel safety supply power, the ambient temperature, and the 6A peak sink current rating.

UCC20225-Q1 UCC20225A-Q1 fig31_luscj9.gifFigure 33. Simplified Representation of Active Pull Down Feature

The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is ground noise from the power supply. This also allows the device to accept small drops in bias voltage, which occurs when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC20225-Q1 family also has an internal under voltage lock out (UVLO) protection feature. The device isn't active unless the voltage at VCCI exceeds VVCCI_ON. A signal will cease to be delivered when VCCI receives a voltage less than VVCCI_OFF. As with the UVLO for VDD, there is hystersis (VVCCI_HYS) to ensure stable operation.

If PWM is active before VCCI or VDD have crossed above their respective on thresholds, the output will not update until 50µs (typical) after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or VDD receive a voltage less than their respective UVLO off thresholds, there is <1µs delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to ensure safe operation during VCCI or VDD brownouts.

The UCC20225-Q1 family can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.

Table 1. UCC20225-Q1 family VCCI UVLO Feature Logic

CONDITION INPUT OUTPUTS
PWM OUTA OUTB
VCCI-GND < VVCCI_ON during device start up H L L
VCCI-GND < VVCCI_ON during device start up L L L
VCCI-GND < VVCCI_OFF after device start up H L L
VCCI-GND < VVCCI_OFF after device start up L L L

Table 2. UCC20225-Q1 family VDD UVLO Feature Logic

CONDITION INPUT OUTPUTS
PWM OUTA OUTB
VDD-VSS < VVDD_ON during device start up H L L
VDD-VSS < VVDD_ON during device start up L L L
VDD-VSS < VVDD_OFF after device start up H L L
VDD-VSS < VVDD_OFF after device start up L L L