10.2.2.4 Estimate Gate Driver Power Loss

The total loss, P_G, in the gate driver subsystem includes the power losses of the UCC20225-Q1 family (P_GD) and the power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not included in P_G and not discussed in this section.

P_GD is the key power loss which determines the thermal safety-related limits of the UCC20225-Q1 family, and it can be estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. P_GDQ is measured on the bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and ambient temperature. Figure 4 shows the per output channel current consumption vs. operating frequency with no load. In this example, V_VCCI = 5 V and V_VDD = 12 V. The current on each power supply, with PWM switching from 0 V to 3.3 V at 200 kHz is measured to be I_VCCI = 2 mA, and I_VDDA = I_VDDB = 1.5 mA. Therefore, the P_GDQ can be calculated with

Equation 11.

The second component is switching operation loss, P_GDO, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, P_GSW, can be estimated with

Equation 12.

where

• Q_G is the gate charge of the power transistor.

If a split rail is used to turn on and turn off, then VDD is the total difference between the positive rail to the negative rail.

So, for this example application:

Equation 13.

Q_G represents the total gate charge of the power transistor switching 400 V at 14 A, and is subject to change with different testing conditions. The UCC20225-Q1 family's gate driver loss on the output stage, P_GDO, is part of P_GSW. P_GDO will be equal to P_GSW if the external gate driver resistances and power transistor internal resistances are 0 Ω, and all the gate driver loss is dissipated inside the UCC20225-Q1 family. If there are external turn-on and turn-off resistance, the total loss will be distributed between the gate driver pull-up/down resistances, external gate resistances, and power transistor internal resistances. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however, it will be non-linear if the source/sink current is saturated. Therefore, P_GDO is different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

Equation 14.

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC20225-Q1 family's gate driver loss can be estimated with:

Equation 15.

Case 2 - Nonlinear Pull-Up/Down Resistor:

Equation 16.

where

• V_OUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off period. In cases where the output is saturated for some time, this can be simplified as a constant current source (4 A at turn-on and 6 A at turn-off) charging/discharging a load capacitor. Then, the V_OUTA/B(t) waveform will be linear and the T_{R_Sys} and T_{F_Sys} can be easily predicted.

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the P_GDO will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-down based on the above discussion.

Total gate driver loss dissipated in the gate driver UCC20225-Q1 family, P_GD, is:

Equation 17.

which is equal to 127 mW in the design example.