JAJSGJ8C November   2018  – September 2019 UCC20225-Q1 , UCC20225A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Thermal Derating Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Propagation Delay and Pulse Width Distortion
    2. 8.2 Rising and Falling Time
    3. 8.3 PWM Input and Disable Response Time
    4. 8.4 Programable Dead Time
    5. 8.5 Power-up UVLO Delay to OUTPUT
    6. 8.6 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in UCC20225-Q1 family
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 Tying the DT Pin to VCC
        2. 9.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing PWM Input Filter
        2. 10.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 10.2.2.3 Gate Driver Output Resistor
        4. 10.2.2.4 Estimate Gate Driver Power Loss
        5. 10.2.2.5 Estimating Junction Temperature
        6. 10.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.6.1 Selecting a VCCI Capacitor
          2. 10.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.6.3 Select a VDDB Capacitor
        7. 10.2.2.7 Dead Time Setting Guidelines
        8. 10.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 関連リンク
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 認定
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

NPL Package
13-Pin LGA
Top View
UCC20225-Q1 UCC20225A-Q1 pin_sluscv8.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
DISABLE 5 I Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when connecting to a micro controller with distance.
DT 6 I Programmable dead time function.

Tying DT to VCCI disables the DT function with dead time ≈ 0ns. Placing a resistor (RDT) between DT and GND adjusts dead time according to: DT (in ns) = 10 x RDT (in kΩ). It is recommended to parallel a ceramic capacitor, 2.2nF or above, close to DT pin to achieve better noise immunity when using RDT.
GND 1 G Primary-side ground reference. All signals in the primary side are referenced to this ground.
NC 3 – No internal connection.
OUTA 12 O Output of driver A. Connect to the gate of the A channel FET or IGBT. Output A is in phase with PWM input with a propagation delay
OUTB 9 O Output of driver B. Connect to the gate of the B channel FET or IGBT. Output B is always complementary to output A with a programmed dead time.
PWM 2 I PWM input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open.
VCCI 4 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible.
VCCI 7 P This pin is internally shorted to pin 4. Preference should be given to bypassing pin-4 to pin-1 instead of pin-7 to pin-1.
VDDA 13 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible.
VDDB 10 P Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located as close to the device as possible.
VSSA 11 G Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB 8 G Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1) P =Power, G= Ground, I= Input, O= Output