JAJSDC3A June   2017  – August 2018 UCC27712

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      標準的な伝播遅延の比較
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dynamic Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD and Under Voltage Lockout
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Level Shift
      6. 8.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 8.3.7 Parasitic Diode Structure
    4. 8.4 Device Functional Modes
      1. 8.4.1 Minimum Input Pulse Operation
      2. 8.4.2 Output Interlock and Dead Time
      3. 8.4.3 Operation Under 100% Duty Cycle Condition
      4. 8.4.4 Operation Under Negative HS Voltage Condition
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 9.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 9.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 9.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 9.2.2.5 Selecting Gate Resistor RON/ROFF
        6. 9.2.2.6 Selecting Bootstrap Diode
        7. 9.2.2.7 Estimate the UCC27712 Power Losses (PUCC27712)
        8. 9.2.2.8 Estimating Junction Temperature
        9. 9.2.2.9 Operation With IGBT's
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Dynamic Electrical Characteristics

At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +125°C (unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DYNAMIC CHARACTERISTICS
tPDLH Turn-on propagation delay (without deadtime) LI to LO, HI to HO, HS = COM = 0 V 100 160 ns
tPDHL Turn-off propagation delay LI to LO, HI to HO, HS = COM = 0 V 100 160
tPDRM Low-to-high delay matching 5 30
tPDFM High-to-low delay matching 12 30
tRISE Turn-on rise time 10% to 90%, HO/LO with 1000-pF load 16 50
tFALL Turn-off fall time 10% to 90%, HO/LO with 1000-pF load 10 30
tON Minimum HI/LI ON pulse that changes output state 0-V to 5-V input signal on HI and LI pins 25 45
tOFF Minimum HI/LI OFF pulse that changes output state 5-V to 0-V input signal on HI and LI pins 35 45
DT Deadtime Internal deadtime for Interlock 100 150 200
UCC27712 typtest_slusce9.gifFigure 1. Typical Test Timing Diagram