JAJSF22D July   2013  – March 2018 UCC28740

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      アプリケーション概略図
      2.      代表的なV-I図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
      2. 7.3.2 Valley-Switching and Valley-Skipping
      3. 7.3.3 Startup Operation
      4. 7.3.4 Fault Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      2. 7.4.2 Primary-Side Constant-Current (CC) Regulation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Standby Power Estimate and No-Load Switching Frequency
        3. 8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
        4. 8.2.2.4 Transformer Turns-Ratio, Inductance, Primary Peak Current
        5. 8.2.2.5 Transformer Parameter Verification
        6. 8.2.2.6 VS Resistor Divider, Line Compensation
        7. 8.2.2.7 Output Capacitance
        8. 8.2.2.8 VDD Capacitance, CVDD
        9. 8.2.2.9 Feedback Network Biasing
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 VDD Pin
      2. 10.1.2 VS Pin
      3. 10.1.3 FB Pin
      4. 10.1.4 GND Pin
      5. 10.1.5 CS Pin
      6. 10.1.6 DRV Pin
      7. 10.1.7 HV Pin
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
      2. 11.1.2 デバイスの項目表記
        1. 11.1.2.1  容量項(ファラッド単位)
        2. 11.1.2.2  デューティ・サイクル項
        3. 11.1.2.3  周波数項(ヘルツ単位)
        4. 11.1.2.4  電流項(アンペア単位)
        5. 11.1.2.5  電流および電圧のスケーリング項
        6. 11.1.2.6  変圧器の項
        7. 11.1.2.7  電力項(ワット単位)
        8. 11.1.2.8  抵抗項(オーム単位)
        9. 11.1.2.9  タイミング項(秒単位)
        10. 11.1.2.10 電圧項(ボルト単位)
        11. 11.1.2.11 AC電圧項(VRMS単位)
        12. 11.1.2.12 効率項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Standby Power Estimate and No-Load Switching Frequency

Assuming minimal no-load standby power is a critical design requirement, determine the estimated no-load power loss based on an accounting of all no-load operating and leakage currents at their respective voltages. Close attention to detail is necessary to account for all of the sources of leakage, however, in many cases, prototype measurement is the only means to obtain a realistic estimation of total primary and secondary leakage currents. At present, converter standby power is certified by compliance-agency authorities based on steady-state room-temperature operation at the highest nominal input voltage rating (typically 230 Vrms).

Equation 6 estimates the standby power loss from the sum of all leakage currents of the primary-side components of the converter. These leakage currents are measured in aggregate by disconnecting the HV input of the controller from the bulk-voltage rail to prevent operating currents from interfering with the leakage measurement.

Equation 6. UCC28740 q_Pprisb_lusbf3.gif

Equation 7 estimates the standby power loss from the sum of all leakage and operating currents of the secondary-side components on the output of the converter. Leakage currents result from reverse voltage applied across the output rectifier and capacitors, while the operating current includes currents required by the shunt-regulator, optocoupler, and associated components.

Equation 7. UCC28740 q_Psecsb_lusbf3.gif

Equation 8 estimates the standby power loss from the sum of all leakage and operating currents of the auxiliary-side components on the controller of the converter. Leakage currents of the auxiliary diode and capacitor are usually negligible. The operating current includes the wait-state current, IWAIT, of the UCC28740 controller, plus the optocoupler-output current for the FB network in the steady-state no-load condition. The VDD voltage in the no-load condition VVDDNL are the lowest practicable value to minimize loss.

Equation 8. UCC28740 q_Pauxsb_lusbf3.gif

Note that PPRI_SB is the only loss that is not dependent on transformer conversion efficiency. PSEC_SB and PAUX_SB are processed through the transformer and incur additional losses as a consequence. Typically, the transformer no-load conversion efficiency ηSWNL lies in the range of 0.50 to 0.70. Total standby input power (no-load condition) is estimated by Equation 9.

Equation 9. UCC28740 q_Psbtot_lusbf3.gif

Although the UCC28740 is capable of operating at the minimum switching frequency of 170 Hz, a typical converter is likely to require a higher frequency to sustain operation at no-load. An accurate estimate of the no-load switching frequency fSWNL entails a thorough accounting of all switching-related energy losses within the converter including parasitic elements of the power-train components. In general, fSWNL is likely to lie within the range of 400 Hz to 800 Hz. A more detailed treatment of standby power and no-load frequency is beyond the scope of this data sheet.