JAJSE40A October   2017  – February 2018 UCC28780


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
      2.      45W、20VのGaN-ACFアダプタの効率
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. Brown-In and Brown-Out
        2. Output Over-Voltage Protection
        3. Over-Temperature Protection
        4. Programmable Over-Power Protection
        5. Peak Current Limit
        6. Output Short-Circuit Protection
        7. Over-Current Protection
        8. Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. Protections on CS pin Fault
        2. Protections on HVG pin Fault
        3. Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Input Bulk Capacitance and Minimum Bulk Voltage
        2. Transformer Calculations
          1. Primary-to-Secondary Turns Ratio (NPS)
          2. Primary Magnetizing Inductance (LM)
          3. Primary Turns (NP)
          4. Secondary Turns (NS)
          5. Turns of Auxiliary Winding (NA)
          6. Winding and Magnetic Core Materials
        3. Clamp Capacitor Calculation
        4. Bleed-Resistor Calculation
        5. Output Filter Calculation
        6. Calculation of ZVS Sensing Network
        7. Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報



  • D|16
  • RTE|16

BUR Pin (Programmable Burst Mode)

The voltage at the BUR pin (VBUR) sets a target peak current threshold (VCST(BUR)) which programs the onset of adaptive burst mode (ABM) and determines the clamped peak current level of switching cycles in each burst packet. When VBUR is designed higher, ABM will start at heavier output load conditions with higher peak current, so the benefit is the higher light-load efficiency but the side effect is a larger burst output voltage ripple. Therefore, 50% to 60% of output load at high line is the recommended highest load condition entering into ABM (Io(BUR)) for both Si and GaN-based ACF designs. The gain between VBUR and VCST(BUR) is a constant gain of KBUR-CST, so setting VCST(BUR) just requires properly selecting the resistor divider on the BUR pin formed by RBUR1 and RBUR2. VBUR should be set between 0.7 V and 2.4 V. If VBUR is less than 0.7 V, VCST(BUR) holds at 0.7 V / KBUR-CST. If VBUR is higher than 2.4 V, VCST(BUR) stays at 2.4 V / KBUR-CST.

Equation 1. UCC28780 Equ-RBUR2.gif

In order to enhance the mode transition between ABM and Low Power Mode (LPM), a programmable offset voltage (ΔVBUR) is generated on top of the VBUR setting in ABM through an internal 2.7-μA current source (IBUR), as shown in Figure 12. In ABM mode, VBUR is set through the resistor voltage divider to fulfill the target average efficiency. After transition from ABM to LPM, the current source is enabled in LPM and flows out of the BUR pin, so ΔVBUR can be programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

Equation 2. UCC28780 Equ-deltaVBUR.gif
UCC28780 BUR-hyseresis.gifFigure 12. Hysteresis Voltage Generation on BUR Pin

When VBUR becomes higher after transition to LPM, the initial peak magnetizing current in LPM is increased with larger energy per switching cycle in a burst packet, which forces UCC28780 to stay in LPM with a higher feedback current than ABM. If ΔVBUR is designed too small, it is possible that mode toggling between LPM and ABM can occur resulting in audible noise. For that situation, ΔVBUR greater than 100 mV is recommended. To minimize the noise coupling effect on VBUR, a filter capacitor on the BUR pin (CBUR) may be needed. CBUR needs to be properly designed to minimize the delay of generating ΔVBUR in time during mode transition. It is recommended that CBUR should be sized small enough to ensure ΔVBUR settles within 40 μs, corresponding to the burst frequency of 25 kHz in LPM (fLPM). Based on three RC time constants representing 95% of a settled steady state value from a step response, the design guide of CBUR is expressed as

Equation 3. UCC28780 Equ-CBUR.gif