JAJSE40A October 2017 – February 2018 UCC28780
The VDD pin is the primary bias for the internal 5-V REF regulator, internal 11-V HVG regulator, other internal references, and the undervoltage lock-out (UVLO) circuit. As shown in Functional Block Diagram, the UVLO circuit connected to the VDD pin controls three power-path switches among VDD, HVG, and SWS pins, in order to allow QS to be able to perform both VVDD startup and VSW sensing for ZVS control after startup. During startup, SWS and HVG pins are connected to VDD pin allowing an external depletion-mode MOSFET (QS) to charge the VDD capacitor (CVDD) from the switch-node voltage (VSW). After VDD startup competes, the ZVS discriminator block is enabled, so as switching logics. Then, the transformer starts delivering energy to the output capacitor (CO) every switching cycle, so both output voltage (VO) and auxiliary winding voltage (VAUX) increase. As VAUX is high enough, the auxiliary winding will take over to power VVDD. The UVLO circuit provides a turn-on threshold of VVDD(ON) at 17.5 V and turn-off threshold of VVDD(OFF) at 9.8 V. The range can accommodate lower values of VDD capacitor (CVDD) and support shorter power-on delays. 38-V maximum operating level on VVDD alleviates concerns with leakage energy charging of CVDD and gives added flexibility when a varying output voltage must be supported.
As VVDD reaches VVDD(ON) , SWS pin is disconnected from the VDD pin, so the CVDD size has to be sufficient to hold VVDD higher than VVDD(OFF) until the positive auxiliary winding voltage is high enough to take over bias power delivery during VO soft start. Therefore, the calculation of minimum capacitance (CVDD(MIN)) needs to consider the discharging effect from the sink current of the UCC28780 during switching in its run state (IRUN(SW)), the average operating current of driver (IDR), and the average gate charge current of half-bridge FETs (IQg) throughout the longest time of VO soft start (tSS(MAX)).
tSS(MAX) estimation should consider the averaged soft-start current (ISEC(SS)) on the secondary side of ACF, the constant-current output load (IO(SS)) (if any), maximum output capacitance (CO(MAX)), and a 1-ms time-out potentially being triggered in the startup sequence.
During VO soft start, VCST reaches the maximum current threshold on the CS pin (VCST(MAX)) , so ISEC(SS) at the minimum voltage of the input bulk capacitor (VBULK(MIN)) can be approximated as:
where RCS is the current sense resistor, NPS is primary-to-secondary turns ratio, and VF is the forward voltage drop of the secondary rectifier.
For details of the startup sequencing, one can refer to the Device Functional Modes of this datasheet.