JAJSE40A October 2017 – February 2018 UCC28780
Due to different capacitance non-linearity between Si and GaN power FETs as well as different propagation delays of their drivers, SET pin is provided to program critical parameters of UCC28780 for the two distinctive power stages. Firstly, this pin sets the zero voltage threshold (VTH(SWS)) at the SWS input pin to be two different auto-tuning targets for ZVS control. When SET pin is tied to GND, VTH(SWS) is set at its low level of 4 V for realizing full ZVS, which allows the low-side switch (QL) to be turned on when the switch-node voltage drops close to 0 V. When SET pin is tied to REF pin, VTH(SWS) is set at 9 V for implementing partial ZVS, which makes QL turn on at around 9V. Secondly, this pin generates different PWML-to-PWMH dead-time (tD(PWML-H)) to achieve ZVS on the high-side clamp switch (QH). A fixed 40ns for VSET = 0 V and an adaptive adjustment for VSET = 5 V. Thirdly, this setting also selects the current sense leading edge blanking time (tCSLEB) to accommodate different delays of the gate drivers; 130 ns for VSET = 0 V and 200 ns for VSET = 5 V. Fourthly, the minimum PWML on-time (tON(MIN)) in low-power mode and standby-power mode varies based on the driver capability; 65 ns for VSET = 0 V and 90 ns for VSET = 5 V. Finally, the maximum PWML on-time for detecting CS pin fault (tCSF). tCSF for VSET = 5 V (tCSF1) is set at 2 μs. tCSF for VSET = 0 V (tCSF0) depends on RRDM, which is configured to 1 μs under RRDM < RRDM(TH) and to 2 μs under RRDM ≥ RRDM(TH).