JAJSE40A October 2017 – February 2018 UCC28780
Figure 19 shows the simplified block diagram explaining the ZVS control of UCC28780. A high-voltage sensing network provides the replica of the switch node voltage waveform (VSW) with a limited “visible” voltage range that the SWS pin can handle. The ZVS discriminator identifies the ZVS condition and determines the adjustment direction for the on-time of PWMH (tDM) by detecting if VSW reaches a predetermined ZVS threshold, VTH(SWS), within tZ, where tZ is the targeted zero voltage transition time of VSW controlled by the PWMH-to-PWML dead-time optimizer.
In Figure 19, VSW of the current switching cycle in the dashed line has not reached VTH(SWS) after tZ expires. The ZVS discriminator sends a TUNE signal to increase tDM for the next switching cycle in the solid line, such that the negative magnetizing current (IM-) can be increased to bring VSW down to a lower level in the same tZ. After a few switching cycles, the tDM optimizer settles and locks into ZVS operation of the low-side switch (QL). In steady-state, there is a fine adjustment on tDM, which is the least significant bit (LSB) of the ZVS tuning loop. This small change of tDM in each switching cycle is too small to significantly move the ZVS condition away from the desired operating point. Figure 20 demonstrates how fast the ZVS control can lock into ZVS operation. Before the ZVS loop is settled, UCC28780 starts in a valley-switching mode as tDM is not long enough to create sufficient IM-. Within 15 switching cycles, the ZVS tuning loop settles and begins toggling tDM with an LSB.