JAJSE40A October 2017 – February 2018 UCC28780
The dead-time optimizer in Figure 19 controls the two dead-times: the dead-time between PWMH falling edge and PWML rising edge (tZ), as well as the dead-time between PWML falling edge and PWMH rising edge (tD(PWML-H)).
The adaptive control law for tZ of UCC28780 utilizes the line feed-forward signal to extend tZ as VBULK reduces, as shown in Figure 21. The VS pin senses VBULK through the auxiliary winding voltage (VAUX) when the low-side switch (QL) is on. The auxiliary winding creates a line-sensing current (IVSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (RVS1). Minimum tZ (tZ(MIN)) is set at VBULK(MAX) through the RTZ pin. When IVSL is lower than 666 μA, tZ linearly increases and the maximum tZ extension is 140% of tZ(MIN).
The control law for tD(PWML-H) of UCC28780 is programmable based on the SET pin voltage. When VSET = 0 V, a fixed delay around 40 ns is used to fit a GaN-based ACF with a fast dV/dt on the VSW rising edge. With VSET = 5 V, the dead-time optimization is enabled to intelligently adapt to the effect of nonlinear junction capacitance of Si MOSFETs on the dV/dt of VSW rising edge. The high capacitance region of the COSS curve for the Si QL creates a shallow ramping on VSW after PWML turns off. When COSS of Si QL moves to the low capacitance region with VSW increasing, VSW starts to ramp up very quickly. Since the changing slope varies with different peak magnetizing currents as output load changes, using a fixed dead-time can potentially cause hard-switching on the high-side clamp switch (QH) if the dead-time is not long enough. UCC28780 utilizes the zero crossing detect (ZCD) signal on the auxiliary-winding voltage to identify if VSW overcomes the shallow ramping, and generates a 50-ns delay (tD(VS-PWMH)) before turning on PWMH. This feature allows cycle-by-cycle dead-time adjustment to avoid hard-switching of QH, while providing fast turn-on timing for QH to minimize the body-diode conduction time.