JAJSE40A October   2017  – February 2018 UCC28780

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      45W、20VのGaN-ACFアダプタの効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. 7.4.10.1 Brown-In and Brown-Out
        2. 7.4.10.2 Output Over-Voltage Protection
        3. 7.4.10.3 Over-Temperature Protection
        4. 7.4.10.4 Programmable Over-Power Protection
        5. 7.4.10.5 Peak Current Limit
        6. 7.4.10.6 Output Short-Circuit Protection
        7. 7.4.10.7 Over-Current Protection
        8. 7.4.10.8 Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. 7.4.11.1 Protections on CS pin Fault
        2. 7.4.11.2 Protections on HVG pin Fault
        3. 7.4.11.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Turns (NP)
          4. 8.2.2.2.4 Secondary Turns (NS)
          5. 8.2.2.2.5 Turns of Auxiliary Winding (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Clamp Capacitor Calculation
        4. 8.2.2.4 Bleed-Resistor Calculation
        5. 8.2.2.5 Output Filter Calculation
        6. 8.2.2.6 Calculation of ZVS Sensing Network
        7. 8.2.2.7 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|16
  • RTE|16
サーマルパッド・メカニカル・データ
発注情報

7.4.5 Adaptive Burst Mode (ABM)

As the load current reduces to IO(BUR) where VCS reaches to VCST(BUR) threshold, ABM starts and VCS is clamped. The peak magnetizing current and the switching frequency (fSW) of each switching cycle are fixed for a given input voltage level. VCST(BUR) is programmed by the BUR pin voltage (VBUR). The PWM pattern of ABM is shown in Figure 25. When RUN goes high, a delay time between RUN and PWML (tD(RUN-PWML)) is given to allow both the gate driver and the UCC28780 time to wake up from a wait state to a run state. PWML is set as the first pulse to build up the bootstrap voltage of the high-side driver before PWMH starts switching. The first PWML pulse turns on QL close to a valley point of the DCM ringing on the switch-node voltage (VSW) by sensing the condition of zero crossing detection (ZCD) on the auxiliary winding voltage (VAUX). The following switching cycles operate in a ZVS condition, since PWMH is enabled. As the number of PWML pulses (NSW) in the burst packet reaches its target value, the RUN pin pulls low after the ZCD of the last switching cycle is detected, and forces the half-bridge driver and UCC28780 into a wait state for the quiescent current reduction of both devices. In this mode, the minimum off-time of the RUN signal is 2.2 µs and the minimum on-time of PWML is limited to the leading-edge blanking time (tCSLEB) of the peak current loop. However, more grouped pulses means more risk of higher output ripple and higher audible noise. The following equation estimates how burst frequency (fBUR) varies with output load and other parameters.

Equation 11. UCC28780 Equ-FBUR.gif

As IO < IO(BUR), fBUR can become lower than the audible noise range if NSW is fixed. In ABM, NSW is modulated to ensure fBUR stays above 20 kHz by monitoring fBUR in each burst period. As IO reduces, fBUR becomes lower and reaches a predetermined low-level frequency threshold (fBUR(LR)) of 25 kHz. The ABM loop commands Nsw of both PWML and PWMH to be reduced by one pulse to maintain fBUR above fBUR(LR). At the same time, the burst frequency ripple on the output voltage reduces as NSW drops with the load reduction. As IO increases, fBUR becomes higher and reaches a predetermined high-level frequency threshold (fBUR(UP)) of 34 kHz. The ABM loop commands NSW to be increased by one pulse to push fBUR back below fBUR(UP).

This algorithm maximizes the number of pulses in each burst packet to improve light-load efficiency, while also limiting the burst output ripple and audible noise. As IO moves below the boundary between AAM and ABM, the maximum NSW is nine and the minimum NSW is two. As IO is close to the boundary between AAM and ABM, the maximum NSW can be higher than nine, to provide a smoother mode transition. When the load slightly increases in this boundary, more than nine pulses are generated in a burst packet as Figure 26 shows. fBUR starts to move lower than 20kHz. The burst pattern with disordered NSW and inconsistent fBUR among the asymmetric burst packets generates a frequency spreading effect to weaken the strength of potential audible noise, when the controller operates in the transition region. It is found that dip varnishing the transformer is a very effective way to mitigate the minor audible noise around the mode transition. ABM operation with lower peak magnetizing current through lower BUR-pin voltage can also help to minimize the potential audible noise. Generally speaking, entering ABM at around 50 to 60% of output load and using a varnished transformer provides good balance between the light-load efficiency and smooth mode transitions with minimal audible noise.

UCC28780 PWM-Pattern-in-ABM.gifFigure 25. PWM Pattern in ABM
UCC28780 AAMABM-transition.gifFigure 26. Mode Transition Behavior between AAM and ABM