JAJSE40A October 2017 – February 2018 UCC28780
The VS pin senses the negative voltage level of the auxiliary winding during the on-time of low-side switch (QL) to detect an under-voltage condition of the input AC line. When the bulk voltage (VBULK) is too low, UCC28780 stops switching and no VO restart attempt is made until the AC input line voltage is back into normal range. As QL turns on with PWML, the negative voltage level of auxiliary winding voltage (VAUX) is equal to VBULK divided by primary-to-auxiliary turns ratio (NPA) of the transformer, which is NP / NA,. During this time, the voltage on VS pin is clamped to about 250 mV below GND. As a result, VAUX can create a line-sensing current (IVSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (RVS1). With IVSL proportional to VBULK, it can be used to compare against two under-voltage thresholds, IVSL(RUN) and IVSL(STOP).
The target brown-in AC voltage (VAC(BI)) can be programmed by the proper selection of RVS1. For every UVLO cycle of VDD, there are at least four initial test pulses from PWML to check IVSLcondition. IVSL of the first test pulse is ignored. If IVSL ≤ IVSL(RUN) is valid for the rest three consecutive test pulses, the controller stops switching, the RUN pin goes low, and a new UVLO start cycle is initiated after VVDD reaches VVDD(OFF). On the other hand, if IVSL > IVSL(RUN) occurs, VO soft start sequence is initiated.
The brown-out AC voltage (VAC(BO)) is set internally by around 83% of VAC(BI), which provides enough hysteresis to compensate for possible sensing errors through the auxiliary winding. A 60-ms timer (tBO) is used to bypass the effect of line ripple content on the IVSL sensing. Only when the IVSL ≤ IVSL(STOP) condition lasts longer than 60 ms, i.e. typically three line cycles of 50 Hz, the brown-out fault is triggered. The fault is reset after VVDD reaches VVDD(OFF). Figure 31 shows an example of the timing sequence of brown-in and brown-out protections.