JAJSE40A October 2017 – February 2018 UCC28780
UCC28780 identifies a fail-short event on the CS pin by monitoring the on-time pulse width of the first PWML pulse after VVDD startup is completed. As shown in Figure 30, the normal first on-time pulse width should be limited by the clamped VCST(SM1) level of 0.28 V and the rising slope of the current-loop feedback signal from the current-sense resistor (RCS) to the CS pin. When the current feedback path is gone due to a CS pin short to GND, the peak magnetizing current increases and potentially can damage the power stage. Therefore, a maximum on-time of the first PWML pulse under VSET = 5 V, tCSF1 of 2 μs in the electrical table, is used to limit the first peak-current stress of the silicon-based converter and then will trigger a CS pin short protection which initiates the tFDR recovery of 1.5 s.
Additionally, tCSF0 in the electrical table confines the maximum on-time of the first PWML pulse on the GaN-based converter with VSET = 0 V. There are two corresponding values based on two predetermined ranges of the RDM pin setting in order to provide the protection over a wider switching frequency range. Specifically, tCSF0 is set at 2 μs with RRDM higher than the RRDM(TH) threshold of 50 kΩ, while tCSF0 is reduced to 1 μs under RRDM < RRDM(TH). Since a GaN-based converter is capable of operating at higher switching frequency by lowering the magnetizing inductance (LM), it is possible that the peak current can increase higher than a lower switching-frequency design under the same VCST(SM1) level and same on-time of PWML. The RDM pin can provide a good indication on the switching frequency range of a GaN power stage, since the lower LM requires smaller RRDM setting. With a different tCSF0 setting, the CS pin fault adapts to a wide switching frequency range.
Unlike a CS pin short protection which senses the first on-time pulse width of PWML only, CS pin open protection monitors the fail-open condition cycle-by-cycle. An internal 4-μA current source out of the CS pin is used to pull the CS pin voltage up to 3.3 V as the CS pin exhibits high impedance during a fail-open condition. When the CS voltage is higher than the 1.2-V threshold of the OCP limit and lasts for three consecutive PWML pulses, the CS pin open protection is triggered which initiates the 1.5-s recovery.