JAJSE40A October 2017 – February 2018 UCC28780
There are four components in the application circuit to help the depletion MOSFET (QS) perform ZVS sensing safely, CSWS, RSWS, DSWS, and RHVG. Design considerations and selection guidelines for the values of these components are given here.
At the rising edge of the switch node, the fast dV/dt coupling through the drain-to-source capacitance of QS (COSS(Qs)) generates a charge current flowing into the capacitive loading of the QS source pin. The result is a voltage overshoot on both the SWS pin and across the gate-to-source of QS (VGS(Qs)). The SWS pin, with an absolute maximum voltage of 38 V, can handle higher voltage stress than VGS(Qs). Therefore, a capacitor between the SWS pin and GND (CSWS) should be selected properly to prevent the voltage overshoot from damaging the QS gate. Since COSS(Qs) and CSWS form a voltage divider, the minimum CSWS (CSWS(MIN)) can be derived as
where VGS_MAX(Qs) is the de-rated maximum gate-to-source voltage of QS, VHVG is the steady-state voltage level of 11 V, and CDsws is the parasitic capacitance of TVS diode (DSWS) on the SWS pin.
Without resistive damping, both the charge current on the rising edge of VSW and the discharge current on the falling edge of VSW are oscillatory with the parasitic inductance within the ZVS sensing network resonating with CSWS. Therefore, a series resistor (RSWS) between SWS pin and source-pin of QS is used to dampen the high-frequency ringing, helping to obtain a cleaner sensing signal on the SWS pin and preventing any high-frequency current from interfering with other noise-sensitive signals. RSWS can be expressed as:
where LSWS is the lumped parasitic inductance including the packaging of QS and PCB traces of QS and CSWS return path.
Based on the above design guide, even though RSWS and CSWS may be sufficient to manage the voltage overshoot in normal operation, a low-capacitance TVS diode (DSWS) is still highly recommended to serve as a safety backup of the ZVS sensing network. A regular Zener diode is not suitable due to its high capacitance and slow clamping response.
Based on the above equations, a general recommendation is that a 50 V C0G-type ceramic capacitor of 22 pF for CSWS, a chip resistor no higher than 120 Ω for RSWS, and a TVS diode with the clamp voltage between 18 V to 24 V for DSWS. Too large of RSWS or CSWS introduces a sensing delay between VSW and SWS pin, so the ZVS control pulls down VSW earlier than expected before the end of tZ by unnecessarily extending tDM. The recommended RSWS and CSWS values only introduce a minor 2.6-ns delay, so the ZVS control is not be affected.
Another issue with too large of RSWS is that an additional voltage drop may be created by the charge current through COSS(Qs) during high dV/dt events of VSW, which becomes another voltage stress onto the gate-to-source voltage of QS . For the power stage that can generate very high dV/dt, lowering RSWS and increasing CSWS may be necessary to enhance the protection on QS. Alternatively, a back-to-back TVS can be added between the gate and source pins of QS to provide a direct clamping to the possible over-voltage stress condition. Furthermore, a high-impedance discharge resistor (RHVG) between the gate and source pins of QS helps to discharge the residual voltage on the gate capacitance, and RHVG around 1 MΩ should be enough to serve the purpose. Note that too small RHVG can hurt standby power, since it creates a continuous current flowing through QS.