SLVSCS1B March   2015  – May 2015 UCD7138

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Body-Diode Conduction Detection
      2. 8.3.2 Gate Turnon and Turnoff
      3. 8.3.3 VCC and Undervoltage Lockout
      4. 8.3.4 Operating Supply Current
      5. 8.3.5 Driver Stage
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Normal Operation Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Half-Bridge LLC
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Gate Input
          2. 9.2.1.1.2 Gate Output
          3. 9.2.1.1.3 Drain-to-Source Voltage Sensing
          4. 9.2.1.1.4 DTC Output
          5. 9.2.1.1.5 Turn-on Edge Optimization
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Design Without SR-Control Optimization
          2. 9.2.1.2.2 Setting the DTC Detection Window
          3. 9.2.1.2.3 Setting the Clamps
          4. 9.2.1.2.4 Setting the DTC Optimization Target and Hysteresis
          5. 9.2.1.2.5 Setting the DTC Negative Current Fault Protection
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resource
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DRS Package
6-Pin WSON With Exposed Thermal Pad
Top View
UCD7138 po_slvscs1.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 IN I Input: Gate driver input. This pin should be connected directly to the DPWM output of the digital controller.
2 DTC O Body-diode conduction-time report: Standard digital IO. Pulled high internally. Output low when the body diode is conducting. This pin should be connected to the DTC0 or DTC1 pin on UCD3138A.
3 VCC P IC supply: External bias supply input. The supply range is 4.5-V to 18-V. A ceramic bypass capacitor of at least 1 µF should be placed as close as possible to the VCC pin and the thermal pad. Where possible, use thick & wide Cu connections.
4 OUT O Gate driver output: Integrated push-pull gate driver for one or more external power MOSFETs. Typical 4-A source and 6-A sink capability. This is a rail-to-rail output, with the rails defined by the voltages on VCC and GND. This pin should be connected to the gate terminal of the synchronous rectification MOSFET.
5 VD I Drain voltage: Connect this pin as close as possible to the controlled-MOSFET drain pad. This pin is internally connected to the diode conduction detection comparator. The comparator has a –0.15-V threshold to detect body-diode conduction. A 20-Ω resistor should be connected between the VD pin and MOSFET drain terminal to limit the current. The maximum voltage of the VD pin should not exceed 45 V. A simple external circuit can enable the usage of much higher voltages, see Figure 34.
6 CTRL I Rising edge optimization control: Connect this pin to ground to disable rising edge optimization. Leave this pin floating or connect it to logic high to enable rising edge optimization.
— Thermal Pad (GND) — Exposed thermal pad: The exposed pad on the bottom of the package enhances the thermal performance of the device. This pad is the device ground reference.