ADS4225 12 ビット、125MSPS、デュアル、低消費電力 AD コンバータ | TIJ.co.jp

ADS4225
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12 ビット、125MSPS、デュアル、低消費電力 AD コンバータ

12 ビット、125MSPS、デュアル、低消費電力 AD コンバータ - ADS4225
データシート
ADS42xx Dual-Channel, 14-/12-Bit, 160/125/65 MSPS Ultralow-Power ADC データシート   （英語）
 

概要

The ADS424x and ADS422x family of devices are low-speed variants of the ADS42xx ultralow-power family of dual-channel, 14-bit/12-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high-dynamic performance, while consuming extremely low power with 1.8-V supply. This topology makes the ADS424x/422x well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS424x/422x have gain options that can be used to improve SFDR performance at lower full-scale input ranges. These devices include a dc offset correction loop that can be used to cancel the ADC offset. Both DDR (double data rate) LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 package.

The devices include internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. All devices are specified over the industrial temperature range (–40°C to 85°C).

特長

  • Ultralow Power With Single 1.8-V Supply, CMOS
    Output:
    • 183 mW Total Power at 65 MSPS
    • 277 mW Total Power at 125 MSPS
    • 332 mW Total Power at 160 MSPS
  • High Dynamic Performance:
    • 88-dBc SFDR at 170 MHz
    • 71.4-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain up to 6 dB for SNR/SFDR
    Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V parallel CMOS Interface
    • Double Data Rate (DDR) LVDS With
      Programmable swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude Down to
    200 mVPP
  • Package: VQFN-64 (9.00 mm × 9.00 mm)

機能一覧

他の製品と比較 高速 ADCs （>10MSPS） メール Excelへダウンロード
Part number オーダー・オプション Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS4225 ご注文 125     Low Power     12     2     70.9     11.3     91     277     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4222 ご注文 65     Low Power     12     2     70.9     11.3     91     183     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4226 ご注文 160     Low Power     12     2     70.9     11.3     91     332     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4229 ご注文 250     Low Power     12     2     70.5     11.15     80.8     470     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4242 ご注文 65     Low Power     14     2     73.6     11.5     91     183     2     DDR LVDS
Parallel CMOS    		 -40 to 85     600     No