ADS4229 12 ビット、250MSPS、2 チャネル、低消費電力 AD コンバータ | TIJ.co.jp

ADS4229
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12 ビット、250MSPS、2 チャネル、低消費電力 AD コンバータ

12 ビット、250MSPS、2 チャネル、低消費電力 AD コンバータ - ADS4229
データシート
 

概要

The ADS4229 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4229 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4229 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available in a compact QFN-64 PowerPAD™ package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4229 is specified over the industrial temperature range (–40°C to +85°C).

特長

  • Maximum Sample Rate: 250 MSPS
  • Ultralow Power with Single 1.8-V Supply:
    • 545-mW Total Power at 250 MSPS
  • High Dynamic Performance:
    • 80.8-dBc SFDR at 170 MHz
    • 69.4-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain Up to 6 dB for
    SNR and SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • DDR LVDS With Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9-mm × 9-mm, 64-Pin Quad Flat
    No-Lead (QFN) Package

機能一覧

他の製品と比較 高速 ADCs (>10MSPS) メール Excelへダウンロード
Part number オーダー・オプション Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS4229 ご注文 250     Low Power     12     2     70.5     11.15     80.8     470     2     DDR LVDS
Parallel CMOS    
-40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4222 ご注文 65     Low Power     12     2     70.9     11.3     91     183     2     DDR LVDS
Parallel CMOS    
-40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4225 ご注文 125     Low Power     12     2     70.9     11.3     91     277     2     DDR LVDS
Parallel CMOS    
-40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4226 ご注文 160     Low Power     12     2     70.9     11.3     91     332     2     DDR LVDS
Parallel CMOS    
-40 to 85     600     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS4242 ご注文 65     Low Power     14     2     73.6     11.5     91     183     2     DDR LVDS
Parallel CMOS    
-40 to 85     600     No