ADS5525 12 ビット 170MSPS ADC、DDR LVDS または パラレル CMOS 選択可能な出力 | TIJ.co.jp

ADS5525
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12 ビット 170MSPS ADC、DDR LVDS または パラレル CMOS 選択可能な出力

12 ビット 170MSPS ADC、DDR LVDS または パラレル CMOS 選択可能な出力 - ADS5525
データシート
 

概要

ADS5525 is a high performance 12-bit, 170-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. Using an internal sample and hold and low jitter clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.

In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. ADS5525 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode.

The device is specified over the industrial temperature range (-40°C to 85°C).

特長

  • Maximum Sample Rate: 170 MSPS
  • 12-Bit Resolution
  • No Missing Codes
  • Total Power Dissipation 1.1 W
  • Internal Sample and Hold
  • 70.5-dBFS SNR at 70-MHz IF
  • 84-dBc SFDR at 70-MHz IF
  • 11 bits ENOB Minimum at 70-MHz IF
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
  • Reduced Power Modes at Lower Sample Rates
  • Supports input clock amplitude down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • No External Reference Decoupling Required
  • Internal and External Reference Support
  • Programmable Output Clock position to ease data capture
  • 3.3-V Analog and Digital Supply
  • 48-QFN Package (7 mm × 7 mm)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

機能一覧

他の製品と比較 高速 ADCs (>10MSPS) メール Excelへダウンロード
Part number オーダー・オプション Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS5525 ご注文 170     High Performance     12     1     71.2     11.5     87     1100     2     Parallel CMOS
Parallel LVDS    
-40 to 85     500     No     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     Catalog     Pipeline    
ADS5527 ご注文 210     Low Power     12     1     70.7     11.4     86     1230     2     Parallel CMOS
Parallel LVDS    
-40 to 85     800     No     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     Catalog     Pipeline    
ADS5545 ご注文 170     High Performance     14     1     74.3     12     90     1100     2     Parallel CMOS
Parallel LVDS    
-40 to 85     500     No     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     Catalog     Pipeline    
ADS5546 ご注文 190     High Performance     14     1     73.8     11.8     90     1130     2     Parallel CMOS
Parallel LVDS    
-40 to 85     500     No     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     Catalog     Pipeline    
ADS5547 サンプルは利用できません。 210     High Performance     14     1     73.6     11.8     87     1230     2.2     Parallel CMOS
Parallel LVDS    
-40 to 85     800     No     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     Catalog     Pipeline