ADS62P19 2チャネル、11 ビット、250/210 MSPS ADC、DDR LVDS およびパラレル CMOS 出力付き | TIJ.co.jp

ADS62P19
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2チャネル、11 ビット、250/210 MSPS ADC、DDR LVDS およびパラレル CMOS 出力付き

 

概要

The ADS62P19 is part of a family of dual-channel, 11-bit, analog-to-digital converters (ADCs) with sampling rates up to 250 MSPS. The device combines high dynamic performance and low power consumption in a compact QFN-64 package. This functionality makes the device well-suited for multi-carrier, wide-bandwidth communication applications.

The ADS62P19 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. The device includes a dc offset correction loop that can be used to cancel ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available.

Although the device includes internal references, the traditional reference pins and associated decoupling capacitors are eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to +85°C).

特長

  • Maximum Sample Rate: 250 MSPS
  • 11-Bit Resolution
  • Total Power: 1.25 W at 250 MSPS
  • Output Options:
    • DDR LVDS and Parallel CMOS
  • Programmable Gain:
    • Up to 6 dB for SNR and SFDR Trade-Off
  • DC Offset Correction
  • Crosstalk: 90 dB
  • Supports Input Clock Amplitude Down to
    400 mVPP, Differential
  • Internal and External Reference Support
  • Package: 9-mm × 9-mm QFN-64

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機能一覧

他の製品と比較 高速 ADCs (>10MSPS) メール Excelへダウンロード
Part number オーダー・オプション Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADS62P19 ご注文 250     High Performance     11     2     66.5     10.6     98     1250     2     DDR LVDS
Parallel CMOS    
-40 to 85     700     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P15 サンプルは利用できません。 125     Low Power     11     2     67.2     10.8     89     740     2     DDR LVDS
Parallel CMOS    
-40 to 85     450     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P22 サンプルは利用できません。 65     High Performance     12     2     71.6     11.5     94     518     2     DDR LVDS
Parallel CMOS    
-40 to 85     450     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P23 サンプルは利用できません。 80     High Performance     12     2     71.6     11.6     93     587     2     DDR LVDS
Parallel CMOS    
-40 to 85     450     No     VQFN | 64     64VQFN: 81 mm2: 9 x 9 (VQFN | 64)     Catalog     Pipeline    
ADS62P24 サンプルは利用できません。 105     High Performance     12     2     71.5     11.5     92     700     2