CDCLVP1102 低ジッタ、1:2、ユニバーサル入力/LVPECL 出力 バッファ | TIJ.co.jp

CDCLVP1102
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低ジッタ、1:2、ユニバーサル入力/LVPECL 出力 バッファ

低ジッタ、1:2、ユニバーサル入力/LVPECL 出力 バッファ - CDCLVP1102
データシート
 

推奨代替製品

  • LMK00304  - このデバイスは類似の機能を備えていますが、同等の機能ではありません。   超低付加ジッタ、LVPECL をサポートできる 1:4 ユニバーサル差動バッファ

概要

The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1102 clock buffer distributes a single clock input (IN) to two pairs of differential LVPECL clock outputs (OUT0, OUT1) with minimum skew for clock distribution. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1102 is characterized for operation from –40°C to 85°C and is available in a QFN-16, 3-mm × 3-mm package.

特長

  • 1:2 Differential Buffer
  • Single Clock Input
  • Universal Inputs Can Accept LVPECL, LVDS,
    LVCMOS/LVTTL
  • Two LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 33 mA
  • Very Low Additive Jitter: <100 fs, RMS in 10-kHz
    to 20-MHz Offset Range
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Output Skew: 10 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Supports 105°C PCB Temperature
    (Measured at Thermal Pad)
  • Available in 3-mm × 3-mm QFN-16 (RGT) Package
  • ESD Protection Exceeds 2 kV (HBM)

Design with CDCLVP1102

Frequency Number of Outputs
 MHz
Output Format

機能一覧

他の製品と比較 差動 メール Excelへダウンロード
Part number オーダー・オプション Additive RMS jitter (Typ) (fs) Output frequency (Max) (MHz) Input type Number of outputs Output type VCC core (V) Operating temperature range (C) VCC out (V)
CDCLVP1102 ご注文 90     2000     LVCMOS
LVDS
LVPECL    
2     LVPECL     2.5
3.3    
-40 to 85     2.5
3.3    
CDCLVP1204 ご注文 57     2000     LVCMOS
LVDS
LVPECL    
4     LVPECL     2.5
3.3    
-40 to 85     2.5
3.3    
CDCP1803 ご注文 150     800     LVPECL     3     LVPECL     3.3     -40 to 85     3.3