The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50- transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS output Y3. This output is delayed by 1.6 ns over the three LVPECL output stages to minimize noise impact during signal transitions.
The CDCM1804 has three control terminals, S0, S1, and S2, to select different output mode settings. The S[2:0] terminals are 3-level inputs and therefore allow up to 33 = 27 combinations. Additionally, an enable terminal (EN) is provided to disable or enable all outputs simultaneously. The EN terminal is a 3-level input as well and extends the number of settings to 2 × 27 = 54.
The CDCM1804 is characterized for operation from -40°C to 85°C.
For use in single-ended driver applications, the CDCM1804 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.
|Part number||オーダー・オプション||Additive RMS jitter (Typ) (fs)||Output frequency (Max) (MHz)||Input type||Number of outputs||Output type||VCC core (V)||VCC out (V)||Operating temperature range (C)|
1-LVCMOS No of outputs = 3 LVPECL
|3.3||3.3||-40 to 85|