LMK00804B 低スキュー、1 ~ 4 多重差動/LVCMOS-LVCMOS/TTL ファンアウト・バッファ | TIJ.co.jp

LMK00804B
この製品はすでに市場にリリースされており、ご購入できます。 一部の製品は、より新しい代替品を使用できる可能性があります。
低スキュー、1 ~ 4 多重差動/LVCMOS-LVCMOS/TTL ファンアウト・バッファ

 

推奨代替製品

  • LMK00101  -  10 出力ユニバーサル LVCMOS バッファ、無故障出力イネーブル付き
  • CDCLVC1310  -  10 出力ユニバーサル LVCMOS バッファ、無故障出力イネーブル付き
  • LMK00725  -  5 出力ユニバーサル LVPECL バッファ、無故障出力イネーブル付き

概要

The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or high-impedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability.

See also Device Comparison Table for descriptions of CDCLVC1310 and LMK00725 parts.

特長

  • Four LVCMOS/LVTTL Outputs with 7 Ω Output
    Impedance
    • Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz
    • Noise Floor: –166 dBc/Hz (typ) @ 125 MHz
    • Output Frequency: 350 MHz (max)
    • Output Skew: 35 ps (max)
    • Part-to-Part Skew: 700 ps (max)
  • Two Selectable Inputs
    • CLK, nCLK Pair Accepts LVPECL, LVDS,
      HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL
    • LVCMOS_CLK Accepts LVCMOS/LVTTL
  • Synchronous Clock Enable
  • Core/Output Power Supplies:
    • 3.3 V/3.3 V
    • 3.3 V/2.5 V
    • 3.3 V/1.8 V
    • 3.3 V/1.5 V
  • Package: 16-Lead TSSOP
  • Industrial Temperature Range: –40ºC to +85ºC

Design with LMK00804B

Frequency Number of Outputs
 MHz
Output Format

機能一覧

他の製品と比較 クロック・バッファ メール Excelへダウンロード
Part number オーダー・オプション Function Additive RMS jitter (Typ) (fs) Output frequency (Max) (MHz) Number of outputs VCC out (V) Features Operating temperature range (C) Rating Output type Package Group Package size: mm2:W x L (PKG) Input type
LMK00804B ご注文 Single-ended     40     350     4     3.3
2.5
1.8
1.5    
Glitch-free output clock     -40 to 85     Catalog     LVCMOS
LVTTL    
TSSOP | 16     16TSSOP: 22 mm2: 4.4 x 5 (TSSOP | 16)     HCSL
LVCMOS
LVDS
LVPECL
LVTTL    
CDCLVC1102 ご注文 Single-ended     70     250     2     2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 8     8TSSOP: 19 mm2: 6.4 x 3 (TSSOP | 8)     LVCMOS    
CDCLVC1103 ご注文 Single-ended     70     250     3     2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 8     8TSSOP: 19 mm2: 6.4 x 3 (TSSOP | 8)     LVCMOS    
CDCLVC1104 ご注文 Single-ended     70     250     4     2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 8     8TSSOP: 19 mm2: 6.4 x 3 (TSSOP | 8)     LVCMOS    
CDCLVC1106 ご注文 Single-ended     70     250     6     2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 14     14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14)     LVCMOS    
CDCLVC1108 ご注文 Single-ended     70     250     8     2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 16     16TSSOP: 22 mm2: 4.4 x 5 (TSSOP | 16)     LVCMOS    
CDCLVC1110 ご注文 Single-ended     70     250     10     2.5
3.3    
  -40 to 85     Catalog     LVCMOS     TSSOP | 20     20TSSOP: 42 mm2: 6.4 x 6.5 (TSSOP | 20)     LVCMOS    
CDCLVC1112 ご注文 Single-ended     70     250     12     2.5
3.3    
  -40 to 85     Catalog     LVCMOS