SLAS897A September 2013  – November 2015 MSP430F5232 , MSP430F5234 , MSP430F5237 , MSP430F5239 , MSP430F5242 , MSP430F5244 , MSP430F5247 , MSP430F5249

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Signal Descriptions
      1. 4.2.1RST/NMI and RSTDVCC/SBWTDIO Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Thermal Characteristics
    7. 5.7 Schmitt-Trigger Inputs - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3, RSTDVCC/SBWTDIO, RST/NMI)
    8. 5.8 Inputs - Interrupts (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9 Leakage Current - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3)
    10. 5.10Outputs - General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3)
    11. 5.11Outputs - General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3)
    12. 5.12Output Frequency - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, P7.0 to P7.5, PJ.0 to PJ.3)
    13. 5.13Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16Crystal Oscillator, XT2
    17. 5.17Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19DCO Frequency
    20. 5.20PMM, Brown-Out Reset (BOR)
    21. 5.21PMM, Core Voltage
    22. 5.22PMM, SVS High Side
    23. 5.23PMM, SVM High Side
    24. 5.24PMM, SVS Low Side
    25. 5.25PMM, SVM Low Side
    26. 5.26Wake-up Times From Low-Power Modes and Reset
    27. 5.27Timer_A
    28. 5.28Timer_B
    29. 5.29USCI (UART Mode) Recommended Operating Conditions
    30. 5.30USCI (UART Mode)
    31. 5.31USCI (SPI Master Mode) Recommended Operating Conditions
    32. 5.32USCI (SPI Master Mode)
    33. 5.33USCI (SPI Slave Mode)
    34. 5.34USCI (I2C Mode)
    35. 5.3510-Bit ADC, Power Supply and Input Range Conditions
    36. 5.3610-Bit ADC, Timing Parameters
    37. 5.3710-Bit ADC, Linearity Parameters
    38. 5.38REF, External Reference
    39. 5.39REF, Built-In Reference
    40. 5.40Comparator_B
    41. 5.41Flash Memory
    42. 5.42JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1 CPU (Link to User's Guide)
    2. 6.2 Operating Modes
    3. 6.3 Interrupt Vector Addresses
    4. 6.4 Memory Organization
    5. 6.5 Bootstrap Loader (BSL)
    6. 6.6 JTAG Operation
      1. 6.6.1JTAG Standard Interface
      2. 6.6.2Spy-Bi-Wire Interface
    7. 6.7 Flash Memory (Link to User's Guide)
    8. 6.8 RAM Memory (Link to User's Guide)
    9. 6.9 Peripherals
      1. 6.9.1 Digital I/O (Link to User's Guide)
      2. 6.9.2 Port Mapping Controller (Link to User's Guide)
      3. 6.9.3 Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4 Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5 Hardware Multiplier (MPY) (Link to User's Guide)
      6. 6.9.6 Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7 Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8 System Module (SYS) (Link to User's Guide)
      9. 6.9.9 DMA Controller (Link to User's Guide)
      10. 6.9.10Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11TA0 (Link to User's Guide)
      12. 6.9.12TA1 (Link to User's Guide)
      13. 6.9.13TA2 (Link to User's Guide)
      14. 6.9.14TB0 (Link to User's Guide)
      15. 6.9.15Comparator_B (Link to User's Guide)
      16. 6.9.16ADC10_A (Link to User's Guide)
      17. 6.9.17CRC16 (Link to User's Guide)
      18. 6.9.18REF Voltage Reference (Link to User's Guide)
      19. 6.9.19Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
      20. 6.9.20Peripheral File Map
    10. 6.10Input/Output Schematics
      1. 6.10.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.10.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.10.3 Port P3, P3.0 to P3.4, Input/Output With Schmitt Trigger
      4. 6.10.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.10.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.10.6 Port P5, P5.2, Input/Output With Schmitt Trigger
      7. 6.10.7 Port P5, P5.3, Input/Output With Schmitt Trigger
      8. 6.10.8 Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
      9. 6.10.9 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      10. 6.10.10Port P7, P7.0 to P7.5, Input/Output With Schmitt Trigger
      11. 6.10.11Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.10.12Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1Device Support
      1. 7.1.1Getting Started and Next Steps
      2. 7.1.2Development Tools Support
        1. 7.1.2.1Hardware Features
        2. 7.1.2.2Recommended Hardware Options
          1. 7.1.2.2.1Target Socket Boards
          2. 7.1.2.2.2Experimenter Boards
          3. 7.1.2.2.3Debugging and Programming Tools
          4. 7.1.2.2.4Production Programmers
        3. 7.1.2.3Recommended Software Options
          1. 7.1.2.3.1Integrated Development Environments
          2. 7.1.2.3.2MSP430Ware
          3. 7.1.2.3.3SYS/BIOS
          4. 7.1.2.3.4Command-Line Programmer
      3. 7.1.3Device and Development Tool Nomenclature
    2. 7.2Documentation Support
    3. 7.3Related Links
    4. 7.4Community Resources
    5. 7.5Trademarks
    6. 7.6Electrostatic Discharge Caution
    7. 7.7Export Control Notice
    8. 7.8Glossary
  8. 8Mechanical, Packaging, and Orderable Information

1 Device Overview

1.1 Features

  • Low Supply-Voltage Range:
    3.6 V Down to 1.8 V
  • Ultra-Low Power Consumption
    • Active Mode (AM):
      All System Clocks Active
      290 µA/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical)
      150 µA/MHz at 8 MHz, 3.0 V, RAM Program Execution (Typical)
    • Standby Mode (LPM3):
      Real-Time Clock (RTC) With Crystal, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:
      1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
      Low-Power Oscillator (VLO), General-Purpose Counter, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:
      1.4 µA at 3.0 V (Typical)
    • Off Mode (LPM4):
      Full RAM Retention, Supply Supervisor Operational, Fast Wakeup:
      1.1 µA at 3.0 V (Typical)
    • Shutdown Mode (LPM4.5):
      0.18 µA at 3.0 V (Typical)
  • Wakeup From Standby Mode in 3.5 µs (Typical)
  • 16-Bit RISC Architecture, Extended Memory, up to 25-MHz System Clock
  • Flexible Power-Management System
    • Fully Integrated LDO With Programmable Regulated Core Supply Voltage
    • Supply Voltage Supervision, Monitoring, and Brownout
  • Unified Clock System
    • FLL Control Loop for Frequency Stabilization
    • Low-Power Low-Frequency Internal Clock Source (VLO)
    • Low-Frequency Trimmed Internal Reference Source (REFO)
    • 32-kHz Watch Crystals (XT1)
    • High-Frequency Crystals up to 32 MHz (XT2)
  • 16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers
  • 16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers
  • 16-Bit Timer TA2, Timer_A With Three Capture/Compare Registers
  • 16-Bit Timer TB0, Timer_B With Seven Capture/Compare Shadow Registers
  • Two Universal Serial Communication Interfaces (USCIs)
    • USCI_A0 and USCI_A1 Each Support:
      • Enhanced UART With Automatic Baud-Rate Detection
      • IrDA Encoder and Decoder
      • Synchronous SPI
    • USCI_B0 and USCI_B1 Each Support:
      • I2C
      • Synchronous SPI
  • 10-Bit Analog-to-Digital Converter (ADC) With Internal Reference, Sample-and-Hold
  • Comparator
  • Hardware Multiplier Supports 32-Bit Operations
  • Serial Onboard Programming, No External Programming Voltage Needed
  • Three-Channel Internal DMA
  • Basic Timer With RTC Feature
  • Section 3 Summarizes the Family Members
  • For Complete Module Descriptions, See the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208)

1.2 Applications

  • Analog Sensor Systems
  • Digital Sensor Systems
  • Data Loggers
  • General-Purpose Applications

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in 3.5 µs (typical).

The MSP430F524x series are microcontroller configurations with four 16-bit timers, a high-performance 10-bit ADC, two USCIs, a hardware multiplier, DMA, a comparator, and an RTC module with alarm capabilities.

The MSP430F523x series microcontrollers include all of the peripherals of the MSP430F524x series except for the ADC.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE(2)
MSP430F5249IRGCVQFN (64)9 mm × 9 mm
MSP430F5249IZQEBGA (80)5 mm × 5 mm
MSP430F5244IRGZVQFN (48)7 mm × 7 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.

1.4 Functional Block Diagrams

Figure 1-1 shows the functional block diagram for the MSP430F5249 and MSP430F5247 devices in the RGC and ZQE packages.

MSP430F5249 MSP430F5247 MSP430F5244 MSP430F5242 MSP430F5239 MSP430F5237 MSP430F5234 MSP430F5232 slas897-block_RGC_ZQE.gif Figure 1-1 Functional Block Diagram – F5249, F5247 – RGC, ZQE Packages

Figure 1-2 shows the functional block diagram for the MSP430F5244 and MSP430F5242 devices in the RGZ package.

MSP430F5249 MSP430F5247 MSP430F5244 MSP430F5242 MSP430F5239 MSP430F5237 MSP430F5234 MSP430F5232 slas897-block_RGZ.gif Figure 1-2 Functional Block Diagram – F5244, F5242 – RGZ Package

Figure 1-3 shows the functional block diagram for the MSP430F5239 and MSP430F5237 devices in the RGC and ZQE packages.

MSP430F5249 MSP430F5247 MSP430F5244 MSP430F5242 MSP430F5239 MSP430F5237 MSP430F5234 MSP430F5232 slas897-block_RGC_ZQE_no_ADC.gif Figure 1-3 Functional Block Diagram – F5239, F5237 – RGC, ZQE Packages

Figure 1-4 shows the functional block diagram for the MSP430F5234 and MSP430F5232 devices in the RGZ package.

MSP430F5249 MSP430F5247 MSP430F5244 MSP430F5242 MSP430F5239 MSP430F5237 MSP430F5234 MSP430F5232 slas897-block_RGZ_no_ADC.gif Figure 1-4 Functional Block Diagram – F5234, F5232 – RGZ Package