SLASE54B March 2016  – January 2017 MSP430FR5962 , MSP430FR5964 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagrams
    2. 4.2Pin Attributes
    3. 4.3Signal Descriptions
    4. 4.4Pin Multiplexing
    5. 4.5Buffer Types
    6. 4.6Connection of Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Typical Characteristics, Active Mode Supply Currents
    6. 5.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8 Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9 Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10Typical Characteristics, Current Consumption per Module
    11. 5.11Thermal Packaging Characteristics
    12. 5.12Timing and Switching Characteristics
      1. 5.12.1 Power Supply Sequencing
      2. 5.12.2 Reset Timing
      3. 5.12.3 Clock Specifications
      4. 5.12.4 Wake-up Characteristics
        1. 5.12.4.1Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.12.5 Digital I/Os
        1. 5.12.5.1Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        2. 5.12.5.2Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6 LEA (Low-Energy Accelerator) (MSP430FR599x Only)
      7. 5.12.7 Timer_A and Timer_B
      8. 5.12.8 eUSCI
      9. 5.12.9 ADC12_B
      10. 5.12.10Reference
      11. 5.12.11Comparator
      12. 5.12.12FRAM
      13. 5.12.13Emulation and Debug
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 CPU
    3. 6.3 Low-Energy Accelerator (LEA) for Signal Processing (MSP430FR599x Only)
    4. 6.4 Operating Modes
      1. 6.4.1Peripherals in Low-Power Modes
      2. 6.4.2Idle Currents of Peripherals in LPM3 and LPM4
    5. 6.5 Interrupt Vector Table and Signatures
    6. 6.6 Bootloader (BSL)
    7. 6.7 JTAG Operation
      1. 6.7.1JTAG Standard Interface
      2. 6.7.2Spy-Bi-Wire Interface
    8. 6.8 FRAM Controller A (FRCTL_A)
    9. 6.9 RAM
    10. 6.10Tiny RAM
    11. 6.11Memory Protection Unit (MPU) Including IP Encapsulation
    12. 6.12Peripherals
      1. 6.12.1 Digital I/O
      2. 6.12.2 Oscillator and Clock System (CS)
      3. 6.12.3 Power-Management Module (PMM)
      4. 6.12.4 Hardware Multiplier (MPY)
      5. 6.12.5 Real-Time Clock (RTC_C)
      6. 6.12.6 Watchdog Timer (WDT_A)
      7. 6.12.7 System Module (SYS)
      8. 6.12.8 DMA Controller
      9. 6.12.9 Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.12.10TA0, TA1, and TA4
      11. 6.12.11TA2 and TA3
      12. 6.12.12TB0
      13. 6.12.13ADC12_B
      14. 6.12.14Comparator_E
      15. 6.12.15CRC16
      16. 6.12.16CRC32
      17. 6.12.17AES256 Accelerator
      18. 6.12.18True Random Seed
      19. 6.12.19Shared Reference (REF)
      20. 6.12.20Embedded Emulation
        1. 6.12.20.1Embedded Emulation Module (EEM) (S Version)
        2. 6.12.20.2EnergyTrace++™ Technology
    13. 6.13Input/Output Diagrams
      1. 6.13.1 Capacitive Touch Functionality on Ports P1 to P8, and PJ
      2. 6.13.2 Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      3. 6.13.3 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.13.4 Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      5. 6.13.5 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      6. 6.13.6 Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      7. 6.13.7 Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      8. 6.13.8 Port P2 (P2.7) Input/Output With Schmitt Trigger
      9. 6.13.9 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      10. 6.13.10Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      11. 6.13.11Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      12. 6.13.12Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      13. 6.13.13Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      14. 6.13.14Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      15. 6.13.15Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      16. 6.13.16Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      17. 6.13.17Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      18. 6.13.18Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      19. 6.13.19Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      20. 6.13.20Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    14. 6.14Device Descriptors (TLV)
    15. 6.15Memory Map
      1. 6.15.1Peripheral File Map
    16. 6.16Identification
      1. 6.16.1Revision Identification
      2. 6.16.2Device Identification
      3. 6.16.3JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1Device Connection and Layout Fundamentals
      1. 7.1.1Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2External Oscillator
      3. 7.1.3JTAG
      4. 7.1.4Reset
      5. 7.1.5Unused Pins
      6. 7.1.6General Layout Recommendations
      7. 7.1.7Do's and Don'ts
    2. 7.2Peripheral- and Interface-Specific Design Information
      1. 7.2.1ADC12_B Peripheral
        1. 7.2.1.1Partial Schematic
        2. 7.2.1.2Design Requirements
        3. 7.2.1.3Detailed Design Procedure
        4. 7.2.1.4Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Export Control Notice
    10. 8.10Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Device Overview

Features

  • Embedded Microcontroller
    • 16-Bit RISC Architecture up to 16‑MHz Clock
    • Up to 256KB of Ferroelectric Random Access Memory (FRAM)
      • Ultra-Low-Power Writes
      • Fast Write at 125 ns Per Word (64KB in 4 ms)
      • Flexible Allocation of Data and Application Code in Memory
      • 1015 Write Cycle Endurance
      • Radiation Resistant and Nonmagnetic
    • Wide Supply Voltage Range:
      1.8 V to 3.6 V (1)
  • Optimized Ultra-Low-Power Modes
    • Active Mode: 118 µA/MHz
    • Standby With VLO (LPM3): 500 nA
    • Standby With Real-Time Clock (RTC) (LPM3.5): 350 nA (2)
    • Shutdown (LPM4.5): 45 nA
  • Low-Energy Accelerator (LEA) for Signal Processing (MSP430FR599x Only)
    • Operation Independent of CPU
    • 4KB of RAM Shared With CPU
    • Efficient 256-Point Complex FFT:
      Up to 40x Faster Than ARM® Cortex®-M0+ Core
  • Intelligent Digital Peripherals
    • 32-Bit Hardware Multiplier (MPY)
    • 6-Channel Internal DMA
    • RTC With Calendar and Alarm Functions
    • Six 16-Bit Timers With up to Seven Capture/Compare Registers Each
    • 32- and 16-Bit Cyclic Redundancy Check (CRC)
  • High-Performance Analog
    • 16-Channel Analog Comparator
    • 12-Bit Analog-to-Digital Converter (ADC) Featuring Window Comparator, Internal Reference and Sample-and-Hold, up to 20 External Input Channels
  • Multifunction Input/Output Ports
    • All Pins Support Capacitive-Touch Capability With No Need for External Components
    • Accessible Bit-, Byte-, and Word-Wise (in Pairs)
    • Edge-Selectable Wake From LPM on All Ports
    • Programmable Pullup and Pulldown on All Ports
  • Code Security and Encryption
    • 128- or 256-Bit AES Security Encryption and Decryption Coprocessor
    • Random Number Seed for Random Number Generation Algorithms
    • IP Encapsulation Protects Memory From External Access
  • Enhanced Serial Communication
    • Up to Four eUSCI_A Serial Communication Ports
      • UART With Automatic Baud-Rate Detection
      • IrDA Encode and Decode
    • Up to Four eUSCI_B Serial Communication Ports
      • I2C With Multiple-Slave Addressing
    • Hardware UART or I2C Bootloader (BSL)
  • Flexible Clock System
    • Fixed-Frequency DCO With 10 Selectable Factory-Trimmed Frequencies
    • Low-Power Low-Frequency Internal Clock Source (VLO)
    • 32-kHz Crystals (LFXT)
    • High-Frequency Crystals (HFXT)
  • Development Tools and Software (Also See Tools and Software)
  • Device Comparison Summarizes the Available Device Variants and Package Options
  • For Complete Module Descriptions, See the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide
Minimum supply voltage is restricted by SVS levels.The RTC is clocked by a 3.7-pF crystal.
The RTC is clocked by a 3.7-pF crystal.
Minimum supply voltage is restricted by SVS levels.

Applications

  • Grid Infrastructure
  • Factory Automation and Control
  • Building Automation
  • Portable Health and Fitness
  • Wearable Electronics

Description

The MSP430FR599x microcontrollers (MCUs) take low power and performance to the next level with the unique Low-Energy Accelerator (LEA) for digital signal processing. This accelerator delivers 40x the performance of ARM® Cortex®-M0+ MCUs to help developers efficiently process data using complex functions such as FFT, FIR, and matrix multiplication. Implementation requires no DSP expertise with a free optimized DSP Library available. Additionally, with up to 256KB of unified memory with FRAM, these devices offer more space for advanced applications and flexibility for effortless implementation of over-the-air firmware updates.

The MSP ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM and a holistic ultra-low-power system architecture, allowing system designers to increase performance while lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and endurance of RAM with the nonvolatile behavior of Flash.

MSP430FR599x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get your design started quickly. Development kits for the MSP430FR599x include the MSP-EXP430FR5994 LaunchPad™ development kit and the MSP-TS430PN80B 80-pin target development board. TI also provides free MSP430Ware™ software, which is available as a component of Code Composer Studio™ IDE desktop and cloud versions within TI Resource Explorer.

Device Information(1)(2)

PART NUMBERPACKAGEBODY SIZE(3)
MSP430FR5994IZVWNFBGA (87)6 mm × 6 mm
MSP430FR5994IPNLQFP (80)12 mm × 12 mm
MSP430FR5994IPMLQFP (64)10 mm × 10 mm
MSP430FR5994IRGZVQFN (48)7 mm × 7 mm
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
For a comparison of all available device variants, see Section 3.
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9.

Functional Block Diagram

Figure 1-1 shows the functional block diagram of the devices.

MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962 bd_Morph.gif
The device has 8KB of RAM, and 4KB of the RAM is shared with the LEA subsystem. The CPU has priority over the LEA subsystem.
The LEA subsystem is available on the MSP430FR599x MCUs only.
Figure 1-1 Functional Block Diagram