SLES248A May   2009  – March 2015 PCM1795

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Digital Filter
      2. 6.7.2 Digital Filter: De-Emphasis Filter
      3. 6.7.3 Analog Dynamic Performance: Supply Voltage Characteristics
      4. 6.7.4 Analog Dynamic Performance: Temperature Characteristics
      5. 6.7.5 Analog FIR Filter performance in DSD Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Data Interface
        1. 7.3.1.1 Audio Serial Interface
        2. 7.3.1.2 PCM Audio Data Formats and Timing
        3. 7.3.1.3 External Digital Filter Interface and Timing
        4. 7.3.1.4 Direct Stream Digital (DSD) Format Interface and Timing
        5. 7.3.1.5 TDMCA Interface
        6. 7.3.1.6 Analog Output
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 System Clock and Reset Functions
        1. 7.5.1.1 System Clock Input
        2. 7.5.1.2 Power-On and External Reset Functions
      2. 7.5.2 Function Descriptions
        1. 7.5.2.1 Zero Detect
      3. 7.5.3 Serial Control Interface
        1. 7.5.3.1 SPI Interface
        2. 7.5.3.2 Register Read/Write Operation
      4. 7.5.4 I2C Interface
        1. 7.5.4.1 Slave Address
        2. 7.5.4.2 Packet Protocol
        3. 7.5.4.3 Write Register
        4. 7.5.4.4 Read Register
        5. 7.5.4.5 Noise Suppression
    6. 7.6 Register Maps
      1. 7.6.1 Mode Control Registers
        1. 7.6.1.1 User-Programmable Mode Controls
        2. 7.6.1.2 Register Map
        3. 7.6.1.3 Register Definitions
          1. 7.6.1.3.1  R/W: Read/Write Mode Select
          2. 7.6.1.3.2  ATx[7:0]: Digital Attenuation Level Setting
          3. 7.6.1.3.3  R/W: Read/Write Mode Select
          4. 7.6.1.3.4  ATLD: Attenuation Load Control
          5. 7.6.1.3.5  FMT[2:0]: Audio Interface Data Format
          6. 7.6.1.3.6  DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
          7. 7.6.1.3.7  DME: Digital De-Emphasis Control
          8. 7.6.1.3.8  MUTE: Soft Mute Control
          9. 7.6.1.3.9  R/W: Read/Write Mode Select
          10. 7.6.1.3.10 REV: Output Phase Reversal
          11. 7.6.1.3.11 ATS[1:0]: Attenuation Rate Select
          12. 7.6.1.3.12 OPE: DAC Operation Control
          13. 7.6.1.3.13 DFMS: Stereo DF Bypass Mode Select
          14. 7.6.1.3.14 FLT: Digital Filter Roll-Off Control
          15. 7.6.1.3.15 INZD: Infinite Zero Detect Mute Control
          16. 7.6.1.3.16 R/W: Read/Write Mode Select
          17. 7.6.1.3.17 SRST: System Reset Control
          18. 7.6.1.3.18 DSD: DSD Interface Mode Control
          19. 7.6.1.3.19 DFTH: Digital Filter Bypass (or Through Mode) Control
          20. 7.6.1.3.20 MONO: Monaural Mode Selection
          21. 7.6.1.3.21 CHSL: Channel Selection for Monaural Mode
          22. 7.6.1.3.22 OS[1:0]: ΔΣ Oversampling Rate Selection
          23. 7.6.1.3.23 R/W: Read/Write Mode Select
          24. 7.6.1.3.24 DZ[1:0]: DSD Zero Output Enable
          25. 7.6.1.3.25 PCMZ: PCM Zero Output Enable
          26. 7.6.1.3.26 R: Read Mode Select
          27. 7.6.1.3.27 ZFGx: Zero-Detection Flag
          28. 7.6.1.3.28 Read Mode Select
          29. 7.6.1.3.29 ID[4:0]: Device ID
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Connection Diagram in PCM Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 I/V Section
          2. 8.2.1.2.2 Differential Section
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Application for External Digital Filter Interface
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Application for Interfacing With an External Digital Filter
          2. 8.2.2.2.2 Pin Assignment When Using the External Digital Filter Interface
          3. 8.2.2.2.3 Audio Format
          4. 8.2.2.2.4 System Clock (SCK) and Interface Timing
          5. 8.2.2.2.5 Functions Available in the External Digital Filter Mode
            1. 8.2.2.2.5.1 FMT[2:0]: Audio Data Format Selection
            2. 8.2.2.2.5.2 OS[1:0]: ΔΣ Modulator Oversampling Rate Selection
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Application for DSD Format (DSD Mode) Interface
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Features
          2. 8.2.3.2.2 Pin Assignment When Using DSD Format Interface
          3. 8.2.3.2.3 Requirements for System Clock
          4. 8.2.3.2.4 DSD Mode Configuration and Function Controls
            1. 8.2.3.2.4.1 Configuration for the DSD Interface Mode
            2. 8.2.3.2.4.2 DMF[1:0]: Analog-FIR Performance Selection
            3. 8.2.3.2.4.3 OS[1:0]: Analog-FIR Operation-Speed Selection
        3. 8.2.3.3 Application Curves
      4. 8.2.4 TDMCA Interface Format
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
          1. 8.2.4.2.1  TDMCA Mode Determination
          2. 8.2.4.2.2  TDMCA Terminals
          3. 8.2.4.2.3  Device ID Determination
          4. 8.2.4.2.4  TDMCA Frame
          5. 8.2.4.2.5  Command Field
            1. 8.2.4.2.5.1 Bit 31: Device ID Enable Flag
            2. 8.2.4.2.5.2 Bit 30: Extended Command Enable Flag
            3. 8.2.4.2.5.3 Bit 29: Daisy-Chain Selection Flag
            4. 8.2.4.2.5.4 Bits[28:24]: Device ID
            5. 8.2.4.2.5.5 Bit 23: Command Read/Write flag
            6. 8.2.4.2.5.6 Bits[22:16]: Register ID
            7. 8.2.4.2.5.7 Bits[15:8]: Command data
            8. 8.2.4.2.5.8 Bits[7:0]: Not used
          6. 8.2.4.2.6  Extended Command Field
          7. 8.2.4.2.7  Audio Fields
          8. 8.2.4.2.8  TDMCA Register Requirements
          9. 8.2.4.2.9  Register Write/Read Operation
          10. 8.2.4.2.10 TDMCA Mode Operation
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

Designers should try to use the same ground between AGND and DGND to avoid any potential voltage difference between them. Ensure that the return currents for digital signals will avoid the AGND pin or the input signals to the I/V stage. Avoid running high-frequency clock and control signals near AGND, or any of the VOUT pins where possible. The pin layout of the PCM1795 device partitions into two sides, the analog side and the digital side. Providing the system is partitioned in such a way that digital signals are routed away from the analog sections, then no digital return currents (for example, clocks) should be generated in the analog circuitry.

  • Decoupling capacitors should be placed as close to the VCC1, VCC2L, VCCR2, VCOML, VCOMR, and VDD pins as possible.
  • Further guidelines can be found in Figure 83.

10.2 Layout Example

PCM1795 layoutexample_sles248.gifFigure 83. Layout Recommendation