SLAS859C May   2012  – May 2015 PCM5100A , PCM5100A-Q1 , PCM5101A , PCM5101A-Q1 , PCM5102A , PCM5102A-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified System Diagram
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings Updated ESD Data
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Requirements, XSMT
    8. 8.8 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Terminology
      2. 9.3.2 Audio Data Interface
        1. 9.3.2.1 Audio Serial Interface
        2. 9.3.2.2 PCM Audio Data Formats
        3. 9.3.2.3 Zero Data Detect
      3. 9.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 9.3.4 Audio Processing
        1. 9.3.4.1 Interpolation Filter
      5. 9.3.5 Reset and System Clock Functions
        1. 9.3.5.1 Clocking Overview
        2. 9.3.5.2 Clock Slave Mode With Master/System Clock (SCK) Input (4 Wire I2S)
        3. 9.3.5.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)
    4. 9.4 Device Functional Modes
      1. 9.4.1 External SCK and PLL Activation
        1. 9.4.1.1 Interpolation Filter Modes
        2. 9.4.1.2 44.1kHz De-emphasis
        3. 9.4.1.3 Audio Format
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Applications
        1. 10.1.1.1 Example Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Distribution and Requirements
    2. 11.2 Recommended Powerdown Sequence
      1. 11.2.1 Planned Shutdown
      2. 11.2.2 Unplanned Shutdown
    3. 11.3 External Power Sense Undervoltage Protection Mode
    4. 11.4 Power-On Reset Function
    5. 11.5 PCM510xA Power Modes
      1. 11.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 11.5.2 Power Save Modes
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Mechanical Data

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
  • PW|20
発注情報

1 Features

  • Ultra Low Out-of-Band Noise
  • Integrated High-Performance Audio PLL with BCK Reference to Generate SCK Internally
  • Direct Line Level 2.1-VRMS Output
  • No DC Blocking Capacitors Required
  • Line Level Output Down to 1KΩ
  • Intelligent Muting System; Soft Up or Down Ramp and Analog Mute For 120-dB Mute SNR
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And BCK Are Deactivated
  • 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
  • Simple Configuration Using Hardware Pins
  • Single-Supply Operation: 14
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Qualified in Accordance with AEC-Q100

2 Applications

  • A/V Receivers, DVD, BD Players
  • Automotive Infotainment and Telematics
  • HDTV Receivers
  • Aftermarket Automotive Amplifiers

3 Description

The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.

Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).

Table 1. Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
PCM5102ATSSOP (20) 5.50 mm × 4.40 mm
PCM5101A
PCM5100A
  1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Simplified System Diagram

PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 pcm1865_pcm510x_sysdiag.gif