製品詳細

Product type Microcontrollers Die or wafer type Known Good Die Rating High Temp Operating temperature range (°C) -55 to 220
Product type Microcontrollers Die or wafer type Known Good Die Rating High Temp Operating temperature range (°C) -55 to 220
DIESALE (KGD) See data sheet
  • High-Performance Static CMOS Technology
  • SM470R1x 16-/32-Bit RISC Core (ARM7TDMI™)
    • 60-MHz System Clock (Pipeline Mode)
    • Independent 16-/32-Bit Instruction Set
    • Open Architecture With Third-Party Support
    • Built-In Debug Module
  • Integrated Memory
    • 1MB Program Flash
      • Two Banks With 16 Contiguous Sectors
    • 64KB Static RAM (SRAM)
    • Memory Security Module (MSM)
    • JTAG Security Module
  • Operating Features
    • Low-Power Modes: STANDBY and HALT
    • Industrial Temperature Range
  • 470+ System Module
    • 32-Bit Address Space Decoding
    • Bus Supervision for Memory/Peripherals
    • Digital Watchdog (DWD) Timer
    • Analog Watchdog (AWD) Timer
    • Enhanced Real-Time Interrupt (RTI)
    • Interrupt Expansion Module (IEM)
    • System Integrity and Failure Detection
    • ICE Breaker
  • Direct Memory Access (DMA) Controller
    • 32 Control Packets and 16 Channels
  • Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock
    Module With Prescaler
    • Multiply-by-4 or -8 Internal ZPLL Option
    • ZPLL Bypass Mode
  • Twelve Communication Interfaces:
    • Two Serial Peripheral Interfaces (SPIs)
    • 255 Programmable Baud Rates
    • Three Serial Communication Interfaces (SCIs)
      • 224 Selectable Baud Rates
      • Asynchronous/Isosynchronous Modes
    • Two High-End CAN Controllers (HECC)
      • 32-Mailbox Capacity
      • Fully Compliant With CAN Protocol, Version
        2.0B
    • Five Inter-Integrated Circuit (I2C) Modules
      • Multi-Master and Slave Interfaces
      • Up to 400 Kbps (Fast Mode)
      • 7- and 10-Bit Address Capability
  • High-End Timer Lite (HET)
    • 12 Programmable I/O Channels:
      • 12 High-Resolution Pins
    • High-Resolution Share Feature (XOR)
    • High-End Timer RAM
      • 64-Instruction Capacity
  • External Clock Prescale (ECP) Module
    • Programmable Low-Frequency External Clock
      (CLK)
  • 12-Channel, 10-Bit Multi-Buffered ADC (MibADC)
    • 64-Word FIFO Buffer
    • Single- or Continuous-Conversion Modes
    • 1.55-µs Minimum Sample and Conversion Time
    • Calibration Mode and Self-Test Features
  • Flexible Interrupt Handling
  • Expansion Bus Module (EBM)
    • Supports 8- and 16-Bit Expansion Bus Memory
      Interface Mappings
    • 42 I/O Expansion Bus Pins
  • 46 Dedicated General-Purpose I/O (GIO) Pins and
    47 Additional Peripheral I/Os
  • Sixteen External Interrupts
  • On-Chip Scan-Base Emulation Logic, IEEE
    Standard 1149.1(1) (JTAG) Test-Access Port
  • Available in KGD, HFQ, HKP, and PGE Packages
  • High-Performance Static CMOS Technology
  • SM470R1x 16-/32-Bit RISC Core (ARM7TDMI™)
    • 60-MHz System Clock (Pipeline Mode)
    • Independent 16-/32-Bit Instruction Set
    • Open Architecture With Third-Party Support
    • Built-In Debug Module
  • Integrated Memory
    • 1MB Program Flash
      • Two Banks With 16 Contiguous Sectors
    • 64KB Static RAM (SRAM)
    • Memory Security Module (MSM)
    • JTAG Security Module
  • Operating Features
    • Low-Power Modes: STANDBY and HALT
    • Industrial Temperature Range
  • 470+ System Module
    • 32-Bit Address Space Decoding
    • Bus Supervision for Memory/Peripherals
    • Digital Watchdog (DWD) Timer
    • Analog Watchdog (AWD) Timer
    • Enhanced Real-Time Interrupt (RTI)
    • Interrupt Expansion Module (IEM)
    • System Integrity and Failure Detection
    • ICE Breaker
  • Direct Memory Access (DMA) Controller
    • 32 Control Packets and 16 Channels
  • Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock
    Module With Prescaler
    • Multiply-by-4 or -8 Internal ZPLL Option
    • ZPLL Bypass Mode
  • Twelve Communication Interfaces:
    • Two Serial Peripheral Interfaces (SPIs)
    • 255 Programmable Baud Rates
    • Three Serial Communication Interfaces (SCIs)
      • 224 Selectable Baud Rates
      • Asynchronous/Isosynchronous Modes
    • Two High-End CAN Controllers (HECC)
      • 32-Mailbox Capacity
      • Fully Compliant With CAN Protocol, Version
        2.0B
    • Five Inter-Integrated Circuit (I2C) Modules
      • Multi-Master and Slave Interfaces
      • Up to 400 Kbps (Fast Mode)
      • 7- and 10-Bit Address Capability
  • High-End Timer Lite (HET)
    • 12 Programmable I/O Channels:
      • 12 High-Resolution Pins
    • High-Resolution Share Feature (XOR)
    • High-End Timer RAM
      • 64-Instruction Capacity
  • External Clock Prescale (ECP) Module
    • Programmable Low-Frequency External Clock
      (CLK)
  • 12-Channel, 10-Bit Multi-Buffered ADC (MibADC)
    • 64-Word FIFO Buffer
    • Single- or Continuous-Conversion Modes
    • 1.55-µs Minimum Sample and Conversion Time
    • Calibration Mode and Self-Test Features
  • Flexible Interrupt Handling
  • Expansion Bus Module (EBM)
    • Supports 8- and 16-Bit Expansion Bus Memory
      Interface Mappings
    • 42 I/O Expansion Bus Pins
  • 46 Dedicated General-Purpose I/O (GIO) Pins and
    47 Additional Peripheral I/Os
  • Sixteen External Interrupts
  • On-Chip Scan-Base Emulation Logic, IEEE
    Standard 1149.1(1) (JTAG) Test-Access Port
  • Available in KGD, HFQ, HKP, and PGE Packages

The SM470R1B1M(3) devices are members of the Texas Instruments SM470R1x family of general-purpose 16-/32-bit reduced instruction set computer (RISC) microcontrollers. The B1M microcontroller offers high performance using the high-speed ARM7TDMI 16-/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16-/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The SM470R1B1M uses the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte of a word is stored at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The B1M RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The B1M devices contain the following:

  • ARM7TDMI 16-/32-bit RISC CPU
  • SM470R1x system module (SYS) with 470+ enhancements
  • 1MB flash
  • 64KB SRAM
  • ZPLL clock module
  • DWD timer
  • AWD timer
  • Enhanced RTI module
  • IEM
  • MSM
  • JTAG security module
  • Two SPI modules
  • Three SCI modules
  • Two HECC
  • Five I2C modules
  • 10-bit MibADC, with 12 input channels
  • HET controlling 12 I/Os
  • ECP
  • EBM
  • Up to 93 I/O pins

The functions performed by the 470+ system module (SYS) include:

  • Address decoding
  • Memory protection
  • Memory and peripherals bus supervision
  • Reset and abort exception management
  • Prioritization for all internal interrupt sources
  • Device clock control
  • Parallel signature analysis (PSA)

The enhanced RTI module on the B1M has the option to be driven by the oscillator clock. The DWD is a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (SPNU189).

The B1M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz or 30 MHz, depending on the input voltage. When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz or 60 MHz, depending on the input voltage. For more detailed information on the flash, see 8.2.1.4.

The MSM and the JTAG security module prevent unauthorized access and visibility to on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code.

The B1M device has twelve communication interfaces: two SPIs, three SCIs, two HECCs, and five I2Cs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The HECC uses a serial, multimaster communication protocol that efficiently supports distributed realtime control with robust communication rates of up to 1 Mbps. These CAN peripherals are ideal for applications operating in noisy and harsh environments (for example, industrial fields) that require reliable serial communication or multiplexed wiring. The I2C module is a multimaster communication module providing an interface between the B1M microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference guides (SPNU195, SPNU196, and SPNU197). For more detailed functional information on the I2C, see the TMS470R1x Inter- Integrated Circuit (I2C) Reference Guide (SPNU223).

The HET is an advanced intelligent timer that provides sophisticated timing functions for realtime applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well-suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (SPNU199).

The B1M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (SPNU199).

The B1M device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (SPNU206).

The ZPLL clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1 to 8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), realtime interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B1M device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (SPNU212).

ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference.

The EBM is a standalone module that supports the multiplexing of the GIO functions and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module (EBM) Reference Guide (SPNU222).

The B1M device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (SPNU202).

The SM470R1B1M(3) devices are members of the Texas Instruments SM470R1x family of general-purpose 16-/32-bit reduced instruction set computer (RISC) microcontrollers. The B1M microcontroller offers high performance using the high-speed ARM7TDMI 16-/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16-/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The SM470R1B1M uses the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte of a word is stored at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The B1M RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The B1M devices contain the following:

  • ARM7TDMI 16-/32-bit RISC CPU
  • SM470R1x system module (SYS) with 470+ enhancements
  • 1MB flash
  • 64KB SRAM
  • ZPLL clock module
  • DWD timer
  • AWD timer
  • Enhanced RTI module
  • IEM
  • MSM
  • JTAG security module
  • Two SPI modules
  • Three SCI modules
  • Two HECC
  • Five I2C modules
  • 10-bit MibADC, with 12 input channels
  • HET controlling 12 I/Os
  • ECP
  • EBM
  • Up to 93 I/O pins

The functions performed by the 470+ system module (SYS) include:

  • Address decoding
  • Memory protection
  • Memory and peripherals bus supervision
  • Reset and abort exception management
  • Prioritization for all internal interrupt sources
  • Device clock control
  • Parallel signature analysis (PSA)

The enhanced RTI module on the B1M has the option to be driven by the oscillator clock. The DWD is a 25-bit resettable decrementing counter that provides a system reset when the watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (SPNU189).

The B1M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz or 30 MHz, depending on the input voltage. When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz or 60 MHz, depending on the input voltage. For more detailed information on the flash, see 8.2.1.4.

The MSM and the JTAG security module prevent unauthorized access and visibility to on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code.

The B1M device has twelve communication interfaces: two SPIs, three SCIs, two HECCs, and five I2Cs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The HECC uses a serial, multimaster communication protocol that efficiently supports distributed realtime control with robust communication rates of up to 1 Mbps. These CAN peripherals are ideal for applications operating in noisy and harsh environments (for example, industrial fields) that require reliable serial communication or multiplexed wiring. The I2C module is a multimaster communication module providing an interface between the B1M microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference guides (SPNU195, SPNU196, and SPNU197). For more detailed functional information on the I2C, see the TMS470R1x Inter- Integrated Circuit (I2C) Reference Guide (SPNU223).

The HET is an advanced intelligent timer that provides sophisticated timing functions for realtime applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well-suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (SPNU199).

The B1M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (SPNU199).

The B1M device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (SPNU206).

The ZPLL clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1 to 8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), realtime interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B1M device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (SPNU212).

ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference.

The EBM is a standalone module that supports the multiplexing of the GIO functions and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module (EBM) Reference Guide (SPNU222).

The B1M device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (SPNU202).

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート SM470R1B1M-HT 16-/32-Bit RISC Flash Microcontroller データシート (Rev. I) PDF | HTML 2015年 6月 16日
* エラッタ TMS470R1B1M TMS470 Microcontrollers Silicon Errata 2005年 9月 12日
* 放射線と信頼性レポート SM470R1B1M-HT Reliability Report 2013年 11月 8日
ユーザー・ガイド ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 2023年 3月 30日
ユーザー・ガイド ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 2023年 3月 30日
ユーザー・ガイド ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 2019年 6月 3日
ユーザー・ガイド ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 2019年 6月 3日
ユーザー・ガイド ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 2018年 11月 19日
ユーザー・ガイド ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 2018年 11月 19日
ユーザー・ガイド ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 2018年 1月 16日
ユーザー・ガイド ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 2018年 1月 16日
ユーザー・ガイド ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 2017年 9月 30日
ユーザー・ガイド ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 2017年 9月 30日
ユーザー・ガイド ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 2017年 6月 21日
ユーザー・ガイド ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 2017年 6月 21日
ユーザー・ガイド ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 2016年 4月 30日
ユーザー・ガイド ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 2016年 4月 30日
EVM ユーザー ガイド (英語) Harsh Environment Acquisition Terminal (H.E.A.T.) System Evaluation Kit (Rev. D) 2015年 7月 24日
ユーザー・ガイド ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 2014年 11月 5日
ユーザー・ガイド ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 2014年 11月 5日
ユーザー・ガイド TMS470R1x Expansion Bus Module (EBM) Reference Guide (Rev. C) 2009年 8月 21日
アプリケーション・ノート TMS470 Expansion Bus Module Example 2006年 12月 20日
ユーザー・ガイド TMS470R1x Memory Security Module (MSM) Reference Guide 2005年 10月 31日
ユーザー・ガイド TMDS-FET470R1B1M IAR Kickstart Development Kit Getting Started Guide 2005年 10月 28日
ユーザー・ガイド TMS470 Peripherals Overview Reference Guide 2005年 10月 22日
ユーザー・ガイド TMS470R1x Multi-Buffered Analog-to-Digital (MibADC) Reference Guide (Rev. C) 2005年 9月 30日
ユーザー・ガイド TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (Rev. E) 2005年 9月 30日
ユーザー・ガイド TMS470R1x Controller Area Network (CAN) Reference Guide (Rev. E) 2005年 7月 30日
ユーザー・ガイド TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (Rev. C) 2005年 2月 11日
ユーザー・ガイド TMS470R1x General-Purpose Input/Output (GIO) Reference Guide (Rev. D) 2005年 1月 31日
ユーザー・ガイド TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (Rev. B) 2004年 11月 1日
ユーザー・ガイド TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (Rev. B) 2004年 11月 1日
ユーザー・ガイド TMS470R1x External Clock Prescale (ECP) Reference Guide (Rev. B) 2004年 11月 1日
ユーザー・ガイド TMS470R1x System Module Reference Guide (Rev. H) 2004年 11月 1日
ユーザー・ガイド TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (Rev. B) 2004年 11月 1日
ユーザー・ガイド TMS470R1x High-End Timer (HET) Reference Guide (Rev. D) 2004年 7月 30日
ユーザー・ガイド TMS470R1x Digital Watchdog Timer Reference Guide 2004年 7月 20日
ユーザー・ガイド TMS470R1x Direct Memory Access (DMA) Controller Reference Guide 2002年 11月 16日
ユーザー・ガイド TMS470R1x Serial Communication Interface (SCI) Reference Guide (Rev. A) 2002年 10月 30日
ユーザー・ガイド TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (Rev. A) 2002年 9月 16日

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

ドライバまたはライブラリ

SPNC006 SM470R1B1M-HT CAN SPI Driver

lock = 輸出許可が必要 (1 分)
サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

製品
ダイ / ウェハー・サービス
SM470R1B1M-HT 高温対応、ARM7TDMI™ フラッシュ マイコン
ドライバまたはライブラリ

SPNC035 Software Peripheral Drivers (SPD)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

製品
ダイ / ウェハー・サービス
SM470R1B1M-HT 高温対応、ARM7TDMI™ フラッシュ マイコン
評価基板 (EVM) 向けの GUI

SLAC498 HEATEVM GUI Software

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

製品
計測アンプ
INA333-HT 高温用、低消費電力、高精度、計測アンプ
ダイ / ウェハー・サービス
SM470R1B1M-HT 高温対応、ARM7TDMI™ フラッシュ マイコン
完全差動アンプ
THS4521-HT 高温、超低消費電力、負のレール入力、レール・ツー・レール出力、差動アンプ
RS-485 と RS-422 の各トランシーバ
SN65HVD11-HT 高温用、3.3V RS-485 トランシーバ
高精度 ADC
ADS1278-HT 高温対応、4/8 入力、同時サンプリング、24 ビット A/D コンバータ
高精度オペアンプ (Vos が 1mV 未満)
OPA211-HT 高温用、1.1nV/√Hz のノイズ、低消費電力、高精度オペアンプ OPA2333-HT 高温対応、1.8V、17μA、2 チャネル、マイクロパワー、ゼロドリフト CMOS オペアンプ
シリーズ電圧リファレンス
REF5025-HT 高温用、低ノイズ、超低ドリフト、高精度電圧リファレンス
複数の CAN トランシーバ
SN65HVD233-HT 高温用、3.3V CAN トランシーバ
ソフトウェア・プログラミング・ツール

SPNC031 Flash API Modules

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サポート対象の製品とハードウェア

製品
ダイ / ウェハー・サービス
SM470R1B1M-HT 高温対応、ARM7TDMI™ フラッシュ マイコン
リファレンス・デザイン

TIDA-00002 — Harsh Environment Acquisition Terminal (HEAT) EVM プラットフォーム、高温アプリケーション用

HEATEVM は、シグナル・コンディショニングおよびプロセッサ評価用の高温プラットフォームを提供することを目的とした MCM です。モジュールを構成する一連のコンポーネントは、最大 200℃ の過酷な動作温度にも耐えられるように設計されています。PCB には、ポリイミド材が使用されており、それらの過酷な温度にも適しています。
試験報告書: PDF
回路図: PDF
パッケージ ピン数 ダウンロード
DIESALE (KGD)

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 材質成分
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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