SN74AUC2G00 デュアル 2 入力正論理 NAND ゲート | TIJ.co.jp

SN74AUC2G00
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デュアル 2 入力正論理 NAND ゲート

デュアル 2 入力正論理 NAND ゲート - SN74AUC2G00
データシート
 

概要

This dual 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC2G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特長

  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 1.2 ns at 1.8 V
  • Low Power Consumption, 10 µA at 1.8 V
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

NanoFree is a trademark of Texas Instruments.

機能一覧

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Part number オーダー・オプション Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Rating Data rate (Max) (Mbps) Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
SN74AUC2G00 ご注文 AUC     0.8     2.7     2     2     9     -9     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Ultra High Speed (tpd <5ns)    
Catalog     250     -40 to 85     8DSBGA: 3 mm2: 2.25 x 1.25 (DSBGA | 8)
8SM8: 12 mm2: 4 x 2.95 (SM8 | 8)
8VSSOP: 6 mm2: 3.1 x 2 (VSSOP | 8)    
DSBGA | 8
SM8 | 8
VSSOP | 8