SN74AUP1G06 低消費電力シングル・インバータ・バッファ/ドライバ、オープンドレイン出力 | TIJ.co.jp

SN74AUP1G06
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低消費電力シングル・インバータ・バッファ/ドライバ、オープンドレイン出力

低消費電力シングル・インバータ・バッファ/ドライバ、オープンドレイン出力 - SN74AUP1G06
データシート
 

推奨代替製品

  • SN74AUC1G06  -  1 回路、インバータ・バッファ/ドライバ、オープン・ドレイン出力付き、高速 - Tpd:2.4ns

Smaller and easy-to-manufacture package option available

This device is now available in a 0.8 x 0.8 x 0.4 (mm) DPW package for space-constrained designs. Order now

概要

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see

AUP – The Lowest-Power Family and Excellent Signal Integrity).

特長

  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 1 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot <10% of VCC
  • Ioff Supports Partial Power-Down-Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 3.6 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications

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機能一覧

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Part number オーダー・オプション Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Package Group
SN74AUP1G06 ご注文 AUP     0.8     3.6     1     4     0     0.9     Standard CMOS     Open-Drain     Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
200     Catalog     DSBGA | 4
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74AUP1G04 ご注文 AUP     0.8     3.6     1     4     -4     0.9     Standard CMOS     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
200     Catalog     DSBGA | 4
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74AUP1G07 ご注文 AUP     0.8     3.6     1     4     0     0.9     Standard CMOS     Open-Drain     Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
200     Catalog     DSBGA | 4
DSBGA | 5
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74LVC1G04 ご注文 LVC     1.65     5.5     1     32     -32     10     Standard CMOS     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Catalog     DSBGA | 4
DSBGA | 5
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74LVC1G06 ご注文 LVC     1.65     5.5     1     32     0     10     Standard CMOS     Open-Drain     Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Catalog     DSBGA | 4
DSBGA | 5
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74LVC1G14 ご注文 LVC     1.65     5.5     1     32     -32     10     Schmitt-Trigger     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff