SN74AUP1G14 低消費電力シングル・シュミットトリガ・インバータ | TIJ.co.jp

SN74AUP1G14
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低消費電力シングル・シュミットトリガ・インバータ

低消費電力シングル・シュミットトリガ・インバータ - SN74AUP1G14
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推奨代替製品

  • SN74AUC1G14  -  1 回路、シュミット-トリガ・インバータ・ゲート、高速 - Tpd:2.4ns

概要

The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity).

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

特長

  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.9 ns Maximum at 3.3 V

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機能一覧

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Part number オーダー・オプション Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Package Group
SN74AUP1G14 ご注文 AUP     0.8     3.6     1     4     -4     0.9     Schmitt-Trigger     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
200     Catalog     DSBGA | 4
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74AUC1G14 ご注文 AUC     0.8     2.7     1     9     -9     10     Schmitt-Trigger     Push-Pull     Balanced outputs
Ultra high speed (tpd <5ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
500     Catalog     DSBGA | 5
SC70 | 5
SOT-23 | 5    
SN74AUP1G17 ご注文 AUP     0.8     3.6     1     4     -4     0.9     Schmitt-Trigger     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
200     Catalog     DSBGA | 4
DSBGA | 5
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74LVC1G14 ご注文 LVC     1.65     5.5     1     32     -32     10     Schmitt-Trigger     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Catalog     DSBGA | 4
DSBGA | 5
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74LVC1G240 ご注文 LVC     1.65     5.5     1     32     -32     10     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Catalog     DSBGA | 5
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5    
SN74LVC2G14 ご注文 LVC     1.65     5.5     2     32     -32     10     Schmitt-Trigger     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs