SN74AUP2G08 低消費電力デュアル 2 入力、正論理 AND ゲート | TIJ.co.jp

SN74AUP2G08 (供給中) 低消費電力デュアル 2 入力、正論理 AND ゲート

低消費電力デュアル 2 入力、正論理 AND ゲート - SN74AUP2G08
データシート
 

推奨代替製品

  • SN74AUC2G08  -  2 回路、2 入力、正 AND ゲート、高速 - Tpd:2.4ns

概要

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

This dual 2-input positive-AND gate performs the Boolean function Y = A • B or Y = A\ + B\ in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特長

  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Max)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typ at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typ)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and
    Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typ at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5.9 ns Max at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

NanoStar is a trademark of Texas Instruments.

機能一覧

他の製品と比較 AND ゲート メール Excelへダウンロード
Part number オーダー・オプション Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) IOH (Max) (mA) Input type Output type Features Data rate (Max) (Mbps) Rating Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
SN74AUP2G08 ご注文 AUP     0.8     3.6     2     2     4     -4     Standard CMOS     Push-Pull     Partial Power Down (Ioff)
Over-Voltage Tolerant Inputs
Very High Speed (tpd 5-10ns)    
100     Catalog     -40 to 85     See datasheet (DSBGA)
8DSBGA: 3 mm2: 2.25 x 1.25 (DSBGA | 8)
8UQFN: 2 mm2: 1.5 x 1.5 (UQFN | 8)
8VSSOP: 6 mm2: 3.1 x 2 (VSSOP | 8)
8X2SON: 1 mm2: 1 x 1.4 (X2SON | 8)    
DSBGA | 8
DSBGA | 8
UQFN | 8
VSSOP | 8
X2SON | 8