SN74LVC1G374-Q1 オートモーティブ・デバイス・カタログ、シングル D タイプ・フリップフロップ、3 ステート出力 | TIJ.co.jp

SN74LVC1G374-Q1
この製品はすでに市場にリリースされており、ご購入できます。 一部の製品は、より新しい代替品を使用できる可能性があります。
オートモーティブ・デバイス・カタログ、シングル D タイプ・フリップフロップ、3 ステート出力

オートモーティブ・デバイス・カタログ、シングル D タイプ・フリップフロップ、3 ステート出力 - SN74LVC1G374-Q1
データシート
 

概要

This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input.

A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特長

  • Qualified for Automotive Applications
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode
    Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78,
    Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

機能一覧

他の製品と比較 D タイプ・フリップフロップ メール Excelへダウンロード
Part number オーダー・オプション Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) Clock Frequency (Max) (MHz) IOL (Max) (mA) IOH (Max) (mA) Features Rating Package Group
SN74LVC1G374-Q1 ご注文 LVC     CMOS/TTL     CMOS     1.65     5.5       32     -32     Ioff
down translation to Vcc
low power    
Automotive     SC70 | 6
SOT-23 | 6    
SN74LVC1G374 ご注文 LVC     CMOS/TTL     CMOS     1.65     5.5       32     -32     Ioff
down translation to Vcc
low power    
Catalog     DSBGA | 6
SC70 | 6
SOT-23 | 6    
SN74LVC1G79 ご注文 LVC     CMOS/TTL     CMOS     1.65     5.5       32     -32     Ioff
down translation to Vcc
low power    
Catalog     DSBGA | 5
SC70 | 5
SOT-23 | 5
SOT-5X3 | 5    
SN74LVC1G79-Q1 ご注文 LVC         1.65     5.5       32     -32     Ioff, Down translation to Vcc, Low Power     Automotive     SC70 | 5    
SN74LVC1G80 ご注文 LVC     CMOS/TTL     CMOS     1.65     5.5       32     -32     Ioff
down translation to Vcc
low power    
Catalog     DSBGA | 5
SC70 | 5
SOT-23 | 5    
SN74LVC1G80-Q1 ご注文 LVC         1.65     5.5     1     32     -32     Ioff, Down translation to Vcc, Low Power     Automotive     SC70 | 5    
SN74LVC2G74-Q1 ご注文 LVC     CMOS/TTL     CMOS     1.65     5.5       32     -32     Ioff
down translation to Vcc
low power    
Automotive     VSSOP | 8