JAJSDR6A August   2017  – September 2017 TIC12400-Q1

PRODUCTION DATA.  

  1. 1     特長
  2. 2     アプリケーション
  3. 3     概要
  4. DeviceImages
    1. 概略回路図
  5. 4     改訂履歴
  6. 5     概要(続き)
  7. 6     Pin Configuration and Functions
    1. Pin Functions
  8. 7     Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8      Parameter Measurement Information
  10. 9     Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VS Pin
      2. 9.3.2  VDD Pin
      3. 9.3.3  Device Initialization
      4. 9.3.4  Device Trigger
      5. 9.3.5  Device Reset
        1. 9.3.5.1 VS Supply POR
        2. 9.3.5.2 Hardware Reset
        3. 9.3.5.3 Software Reset
      6. 9.3.6  VS Under-Voltage (UV) Condition
      7. 9.3.7  VS Over-Voltage (OV) Condition
      8. 9.3.8  Switch Inputs Settings
        1. 9.3.8.1 Input Current Source/Sink Selection
        2. 9.3.8.2 Input Mode Selection
        3. 9.3.8.3 Input Enable Selection
        4. 9.3.8.4 Thresholds Adjustment
        5. 9.3.8.5 Wetting Current Configuration
      9. 9.3.9  Interrupt Generation and INT Assertion
        1. 9.3.9.1 INT Pin Assertion Scheme
        2. 9.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 9.3.9.3 Microcontroller Wake-Up
        4. 9.3.9.4 Interrupt Enable / Disable And Interrupt Generation Conditions
        5. 9.3.9.5 Detection Filter
      10. 9.3.10 Temperature Monitor
        1. 9.3.10.1 Temperature Warning (TW)
        2. 9.3.10.2 Temperature Shutdown (TSD)
      11. 9.3.11 Parity Check And Parity Generation
      12. 9.3.12 Cyclic Redundancy Check (CRC)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Continuous Mode
      2. 9.4.2 Polling Mode
        1. 9.4.2.1 Standard Polling
        2. 9.4.2.2 Matrix polling
      3. 9.4.3 Additional Features
        1. 9.4.3.1 Clean Current Polling (CCP)
        2. 9.4.3.2 Wetting Current Auto-Scaling
        3. 9.4.3.3 VS Measurement
        4. 9.4.3.4 Wetting Current Diagnostic
        5. 9.4.3.5 ADC Self-Diagnostic
    5. 9.5 Programming
      1. 9.5.1 SPI Communication Interface Buses
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 System Clock (SCLK)
        3. 9.5.1.3 Slave In (SI)
        4. 9.5.1.4 Slave Out (SO)
      2. 9.5.2 SPI Sequence
        1. 9.5.2.1 Read Operation
        2. 9.5.2.2 Write Operation
        3. 9.5.2.3 Status Flag
    6. 9.6 REGISTER_MAPS
      1. 9.6.1  DEVICE_ID register (Offset = 1h) [reset = 20h]
        1. Table 12. DEVICE_ID Register Field Descriptions
      2. 9.6.2  INT_STAT Register (Offset = 2h) [reset = 1h]
        1. Table 13. INT_STAT Register Field Descriptions
      3. 9.6.3  CRC Register (Offset = 3h) [reset = FFFFh]
        1. Table 14. CRC Register Field Descriptions
      4. 9.6.4  IN_STAT_MISC Register (Offset = 4h) [reset = 0h]
        1. Table 15. IN_STAT_MISC Register Field Descriptions
      5. 9.6.5  IN_STAT_COMP Register (Offset = 5h) [reset = 0h]
        1. Table 16. IN_STAT_COMP Register Field Descriptions
      6. 9.6.6  IN_STAT_ADC0 Register (Offset = 6h) [reset = 0h]
        1. Table 17. IN_STAT_ADC0 Register Field Descriptions
      7. 9.6.7  IN_STAT_ADC1 Register (Offset = 7h) [reset = 0h]
        1. Table 18. IN_STAT_ADC1 Register Field Descriptions
      8. 9.6.8  IN_STAT_MATRIX0 Register (Offset = 8h) [reset = 0h]
        1. Table 19. IN_STAT_MATRIX0 Register Field Descriptions
      9. 9.6.9  IN_STAT_MATRIX1 Register (Offset = 9h) [reset = 0h]
        1. Table 20. IN_STAT_MATRIX1 Register Field Descriptions
      10. 9.6.10 ANA_STAT0 Register (Offset = Ah) [reset = 0h]
        1. Table 21. ANA_STAT0 Register Field Descriptions
      11. 9.6.11 ANA_STAT1 Register (Offset = Bh) [reset = 0h]
        1. Table 22. ANA_STAT1 Register Field Descriptions
      12. 9.6.12 ANA_STAT2 Register (Offset = Ch) [reset = 0h]
        1. Table 23. ANA_STAT2 Register Field Descriptions
      13. 9.6.13 ANA_STAT3 Register (Offset = Dh) [reset = 0h]
        1. Table 24. ANA_STAT3 Register Field Descriptions
      14. 9.6.14 ANA_STAT4 Register (Offset = Eh) [reset = 0h]
        1. Table 25. ANA_STAT4 Register Field Descriptions
      15. 9.6.15 ANA_STAT5 Register (Offset = Fh) [reset = 0h]
        1. Table 26. ANA_STAT5 Register Field Descriptions
      16. 9.6.16 ANA_STAT6 Register (Offset = 10h) [reset = 0h]
        1. Table 27. ANA_STAT6 Register Field Descriptions
      17. 9.6.17 ANA_STAT7 Register (Offset = 11h) [reset = 0h]
        1. Table 28. ANA_STAT7 Register Field Descriptions
      18. 9.6.18 ANA_STAT8 Register (Offset = 12h) [reset = 0h]
        1. Table 29. ANA_STAT8 Register Field Descriptions
      19. 9.6.19 ANA_STAT9 Register (Offset = 13h) [reset = 0h]
        1. Table 30. ANA_STAT9 Register Field Descriptions
      20. 9.6.20 ANA_STAT10 Register (Offset = 14h) [reset = 0h]
        1. Table 31. ANA_STAT10 Register Field Descriptions
      21. 9.6.21 ANA_STAT11 Register (Offset = 15h) [reset = 0h]
        1. Table 32. ANA_STAT11 Register Field Descriptions
      22. 9.6.22 ANA_STAT12 Register (Offset = 16h) [reset = 0h]
        1. Table 33. ANA_STAT12 Register Field Descriptions
      23. 9.6.23 CONFIG Register (Offset = 1Ah) [reset = 0h]
        1. Table 34. CONFIG Register Field Descriptions
      24. 9.6.24 IN_EN Register (Offset = 1Bh) [reset = 0h]
        1. Table 35. IN_EN Register Field Descriptions
      25. 9.6.25 CS_SELECT Register (Offset = 1Ch) [reset = 0h]
        1. Table 36. CS_SELECT Register Field Descriptions
      26. 9.6.26 WC_CFG0 Register (Offset = 1Dh) [reset = 0h]
        1. Table 37. WC_CFG0 Register Field Descriptions
      27. 9.6.27 WC_CFG1 Register (Offset = 1Eh) [reset = 0h]
        1. Table 38. WC_CFG1 Register Field Descriptions
      28. 9.6.28 CCP_CFG0 Register (Offset = 1Fh) [reset = 0h]
        1. Table 39. CCP_CFG0 Register Field Descriptions
      29. 9.6.29 CCP_CFG1 Register (Offset = 20h) [reset = 0h]
        1. Table 40. CCP_CFG1 Register Field Descriptions
      30. 9.6.30 THRES_COMP Register (Offset = 21h) [reset = 0h]
        1. Table 41. THRES_COMP Register Field Descriptions
      31. 9.6.31 INT_EN_COMP1 Register (Offset = 22h) [reset = 0h]
        1. Table 42. INT_EN_COMP1 Register Field Descriptions
      32. 9.6.32 INT_EN_COMP2 Register (Offset = 23h) [reset = 0h]
        1. Table 43. INT_EN_COMP2 Register Field Descriptions
      33. 9.6.33 INT_EN_CFG0 Register (Offset = 24h) [reset = 0h]
        1. Table 44. INT_EN_CFG0 Register Field Descriptions
      34. 9.6.34 INT_EN_CFG1 Register (Offset = 25h) [reset = 0h]
        1. Table 45. INT_EN_CFG1 Register Field Descriptions
      35. 9.6.35 INT_EN_CFG2 Register (Offset = 26h) [reset = 0h]
        1. Table 46. INT_EN_CFG2 Register Field Descriptions
      36. 9.6.36 INT_EN_CFG3 Register (Offset = 27h) [reset = 0h]
        1. Table 47. INT_EN_CFG3 Register Field Descriptions
      37. 9.6.37 INT_EN_CFG4 Register (Offset = 28h) [reset = 0h]
        1. Table 48. INT_EN_CFG4 Register Field Descriptions
      38. 9.6.38 THRES_CFG0 Register (Offset = 29h) [reset = 0h]
        1. Table 49. THRES_CFG0 Register Field Descriptions
      39. 9.6.39 THRES_CFG1 Register (Offset = 2Ah) [reset = 0h]
        1. Table 50. THRES_CFG1 Register Field Descriptions
      40. 9.6.40 THRES_CFG2 Register (Offset = 2Bh) [reset = 0h]
        1. Table 51. THRES_CFG2 Register Field Descriptions
      41. 9.6.41 THRES_CFG3 Register (Offset = 2Ch) [reset = X]
        1. Table 52. THRES_CFG3 Register Field Descriptions
      42. 9.6.42 THRES_CFG4 Register (Offset = 2Dh) [reset = X]
        1. Table 53. THRES_CFG4 Register Field Descriptions
      43. 9.6.43 THRESMAP_CFG0 Register (Offset = 2Eh) [reset = 0h]
        1. Table 54. THRESMAP_CFG0 Register Field Descriptions
      44. 9.6.44 THRESMAP_CFG1 Register (Offset = 2Fh) [reset = 0h]
        1. Table 55. THRESMAP_CFG1 Register Field Descriptions
      45. 9.6.45 THRESMAP_CFG2 Register (Offset = 30h) [reset = 0h]
        1. Table 56. THRESMAP_CFG2 Register Field Descriptions
      46. 9.6.46 Matrix Register (Offset = 31h) [reset = 0h]
        1. Table 57. Matrix Register Field Descriptions
      47. 9.6.47 Mode Register (Offset = 32h) [reset = 0h]
        1. Table 58. Mode Register Field Descriptions
    7. 9.7 Programming Guidelines
  11. 10    Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 10.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure
      3. 10.3.3 Application Curves
  12. 11    Power Supply Recommendations
  13. 12    Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13    デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  15. 14    メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
  • DCP|38
発注情報

特長

  • 車載アプリケーションに対応
  • 下記内容でAEC-Q100認定済み:
    • デバイス温度グレード 1: 動作時周囲温度        –40℃~125℃
    • デバイスHBM ESD分類レベルH2
    • デバイスCDM ESD分類レベルC4B
  • 過電圧および低電圧警告により、12V車載システムをサポートするように設計
  • 最大24の直接スイッチ入力を監視し、そのうち10の入力はグランドまたはバッテリに接続されているスイッチを監視するよう構成可能
  • スイッチ入力耐性は40V (ロードダンプ状態)~-24V (逆極性状態)
  • 6つの構成可能なウェット電流設定:
    (0mA、1mA、2mA、5mA、10mA、15mA)
  • 内蔵の10ビットADCによるマルチポジション・アナログ・スイッチ監視
  • デジタル・スイッチ監視用に4つのプログラマブル・スレッショルドを備えた内蔵コンパレータ
  • ポーリング・モードでの極めて低い動作電流:
    標準値68μA (tPOLL=64ms、tPOLL_ACT=128μs、
    24の入力がすべてアクティブ、コンパレータ・モード、すべてのスイッチが開)
  • 3.3V/5Vのシリアル・ペリフェラル・インターフェイス(SPI)プロトコルを使用してMCUに直接接続
  • 割り込み生成により、すべての入力でウェークアップ動作をサポート
  • バッテリおよび温度センシングを内蔵
  • 適切な外付けコンポーネントにより、ISO-10605に準拠した入力ピンでの±8kVの接触放電ESD保護を実現
  • 38ピンTSSOPパッケージ