TL071B 低ノイズ JFET 入力オペアンプ | TIJ.co.jp

TL071B
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低ノイズ JFET 入力オペアンプ

低ノイズ JFET 入力オペアンプ - TL071B
データシート
TL07xx Low-Noise JFET-Input Operational Amplifiers データシート   （英語）
 

概要

The TL07xx JFET-input operational amplifiers incorporate well-matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low-input bias and offset currents, and low offset-voltage temperature coefficient. The low harmonic distortion and low noise make the TL07x series ideally suited for high-fidelity and audio pre-amplifier applications. The TL071 device has offset pins to support external input offset correction.

特長

  • Low Power Consumption
  • Wide Common-Mode and Differential Voltage Ranges
  • Low Input Bias and Offset Currents
  • Output Short-Circuit Protection
  • Low Total Harmonic Distortion: 0.003% (Typical)
  • Low Noise
    Vn = 18 nV/√Hz (Typical) at f = 1 kHz
  • High-Input Impedance: JFET Input Stage
  • Internal Frequency Compensation
  • Latch-Up-Free Operation
  • High Slew Rate: 13 V/µs (Typical)
  • Common-Mode Input Voltage Range
    Includes VCC+

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Part number オーダー・オプション Number of channels (#) Total supply voltage (Min) (+5V=5, +/-5V=10) Total supply voltage (Max) (+5V=5, +/-5V=10) GBW (Typ) (MHz) Slew rate (Typ) (V/us) Rail-to-rail Vos (offset voltage @ 25 C) (Max) (mV) Iq per channel (Typ) (mA) Vn at 1 kHz (Typ) (nV/rtHz) Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG) Offset drift (Typ) (uV/C) Features Input bias current (Max) (pA) CMRR (Typ) (dB) Output current (Typ) (mA) Architecture
TL071B ご注文 1     7     30     3     13     In to V+     3     1.4     18     Catalog     0 to 70     PDIP | 8
SOIC | 8    		 8PDIP: 93 mm2: 9.43 x 9.81 (PDIP | 8)
8SOIC: 19 mm2: 3.91 x 4.9 (SOIC | 8)    		 18     Standard Amps     200     100     10     FET