The TMDS361B is a three-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to three DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth. TMDS361B is not intended for source side applications such as external switch boxes.
The TMDS361B provides an adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps.
When any of the input ports are selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.
The TMDS361B is designed to be controlled via a local I2C interface or GPIO interface based on the status of the I2C_SEL pin. The local I2C interface in TMDS361B is a slave-only I2C interface. (See the section.)
I2C Mode: When the I2C_SEL pin is set low, the device is in I2C mode. With local I2C, the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the for detailed description on DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature, and TMDS input-port selection can be set. See through .
GPIO mode: When the I2C_SEL pin is set high, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set, and the default DDC I2C buffer OVS setting (OVS3) is set. See and the for a detailed description of the DDC I2C buffer.
Following are some of the key features (advantages) that TMDS361B provides to the overall sink-side system (HDTV).
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|Part number||オーダー・オプション||ESD HBM (kV)||Protocols||Speed (Max) (Gbps)||Number of TMDS inputs||Supply voltage (V)||Number of TMDS outputs||Package Group||Package size: mm2:W x L (PKG)||Protocols (Typ)||Operating temperature range (C)|
||10||HDMI||3||3||3.3||1||TQFP | 64||64TQFP: 144 mm2: 12 x 12 (TQFP | 64)||HDMI||0 to 70|
||6||HDMI||2.25||1||3.3||1||VQFN | 40||40VQFN: 36 mm2: 6 x 6 (VQFN | 40)||HDMI||0 to 70|
|1||VQFN | 48||48VQFN: 49 mm2: 7 x 7 (VQFN | 48)||HDMI1.4b||
-40 to 85
0 to 70
|1||VQFN | 48||48VQFN: 49 mm2: 7 x 7 (VQFN | 48)||HDMI 2.0||
-40 to 85
0 to 85
||9||HDMI||3||2||3.3||1||TQFP | 64||64TQFP: 144 mm2: 12 x 12 (TQFP | 64)||HDMI||0 to 70|