TMS320C6701 浮動小数点デジタル・シグナル・プロセッサ | TIJ.co.jp

TMS320C6701
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浮動小数点デジタル・シグナル・プロセッサ

浮動小数点デジタル・シグナル・プロセッサ - TMS320C6701
データシート エラッタ
 

推奨代替製品

  • TMS320C6727B  -  このデバイスは機能的には上ですが、ピン同士の互換性がなく、特性が同等ではありません。
  • TMS320C6746  - このデバイスは類似の機能を備えていますが、同等の機能ではありません。 

No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

概要

The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000™ DSP platform. The TMS320C6701 (C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the C6701 offers cost-effective solutions to high-performance DSP programming challenges. The C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

特長

  • Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C6701
    • 8.3-, 6.7-, 6-ns Instruction Cycle Time
    • 120-, 150-, 167-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 1 GFLOPS
    • TMS320C6201 Fixed-Point DSP Pin-Compatible
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C67x™ CPU Core
    • Eight Highly Independent Functional Units:
      • Four ALUs (Floating- and Fixed-Point)
      • Two ALUs (Fixed-Point)
      • Two Multipliers (Floating- and Fixed-Point)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Hardware Support for IEEE Single-Precision Instructions
    • Hardware Support for IEEE Double-Precision Instructions
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • 1M-Bit On-Chip SRAM
    • 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
    • 512K-Bit Dual-Access Internal Data (64K Bytes)
  • 32-Bit External Memory Interface (EMIF) to Synchronous/Asynchronous Memories
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • 52M-Byte Addressable External Memory Space
  • Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 352-Pin Ball Grid Array (BGA) Package (GJC Suffix)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)
  • 3.3-V I/Os, 1.9-V Internal (167-MHz Only)

VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.

機能一覧

他の製品と比較 C6000 浮動小数点 DSP メール Excelへダウンロード
Part number オーダー・オプション DSP On-chip L2 cache/RAM Operating systems DRAM Serial I/O Approx. price (US$) Operating temperature range (C) Rating
TMS320C6701 ご注文 1 C67x     512 KB     DSP/BIOS     SDRAM     McBSP     87.00 | 1ku     0 to 90
-40 to 105    
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