SLASE99A December   2015  – April 2016 TPA3250

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Audio Characteristics (BTL)
    7. 7.7  Audio Characteristics (SE)
    8. 7.8  Audio Characteristics (PBTL)
    9. 7.9  Typical Characteristics, BTL Configuration
    10. 7.10 Typical Characteristics, SE Configuration
    11. 7.11 Typical Characteristics, PBTL Configuration
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Protection System
        1. 9.4.1.1 Overload and Short Circuit Current Protection
        2. 9.4.1.2 DC Speaker Protection
        3. 9.4.1.3 Pin-to-Pin Short Circuit Protection (PPSC)
        4. 9.4.1.4 Overtemperature Protection OTW and OTE
        5. 9.4.1.5 Undervoltage Protection (UVP) and Power-on Reset (POR)
        6. 9.4.1.6 Fault Handling
        7. 9.4.1.7 Device Reset
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 PCB Material Recommendation
          4. 10.2.1.2.4 Oscillator
      2. 10.2.2 Application Curves
      3. 10.2.3 Typical Application, Single Ended (1N) SE
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedures
        3. 10.2.3.3 Application Curves
      4. 10.2.4 Typical Application, Differential (2N) PBTL
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedures
        3. 10.2.4.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 VDD Supply
      2. 11.1.2 GVDD_X Supply
      3. 11.1.3 PVDD Supply
    2. 11.2 Powering Up
    3. 11.3 Powering Down
    4. 11.4 Thermal Design
      1. 11.4.1 Thermal Performance
      2. 11.4.2 Thermal Performance with Continuous Output Power
      3. 11.4.3 Thermal Performance with Non-Continuous Output Power
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
      1. 12.2.1 BTL Application Printed Circuit Board Layout Example
      2. 12.2.2 SE Application Printed Circuit Board Layout Example
      3. 12.2.3 PBTL Application Printed Circuit Board Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DDW|44
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

The TPA3250 is available in a thermally enhanced TSSOP package.

The package type contains a PowerPad™ that is located on the bottom side of the device for thermal connection to the PCB.

DDV Package
HTSSOP 44-Pin
(Top View)

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AVDD 9 P Internal voltage regulator, analog section
BST_A 23 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
BST_B 24 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
BST_C 43 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
BST_D 44 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
CLIP_OTW 2 O Clipping warning and Over-temperature warning; open drain; active low
C_START 8 O Startup ramp, requires a charging capacitor to GND
DVDD 12 P Internal voltage regulator, digital section
FAULT 4 O Shutdown signal, open drain; active low
FREQ_ADJ 15 O Oscillator frequency programming pin
GND 10, 11, 25, 26, 33, 34, 41, 42 P Ground
GVDD_AB 22 P Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
GVDD_CD 1 P Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
INPUT_A 17 I Input signal for half bridge A
INPUT_B 18 I Input signal for half bridge B
INPUT_C 7 I Input signal for half bridge C
INPUT_D 6 I Input signal for half bridge D
M1 20 I Mode selection 1 (LSB)
M2 19 I Mode selection 2 (MSB)
OC_ADJ 16 I/O Over-Current threshold programming pin
OSC_IOM 14 I/O Oscillator synchronization interface
OSC_IOP 13 O Oscillator synchronization interface
OUT_A 27, 28 O Output, half bridge A
OUT_B 32 O Output, half bridge B
OUT_C 35 O Output, half bridge C
OUT_D 39, 40 O Output, half bridge D
PVDD_AB 29, 30, 31 P PVDD supply for half-bridge A and B
PVDD_CD 36, 37, 38 P PVDD supply for half-bridge C and D
RESET 5 I Device reset Input; active low
VDD 21 P Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
VBG 3 P Internal voltage reference requires a 0.1-µF capacitor to GND for decoupling.
PowerPAD™ P Ground, connect to PCB copper pour. Placed on bottom side of device.

Table 1. Mode Selection Pins

MODE PINS INPUT MODE OUTPUT CONFIGURATION DESCRIPTION
M2 M1
0 0 2N + 1 2 × BTL Stereo BTL output configuration
0 1 2N/1N + 1 1 x BTL + 2 x SE 2.1 BTL + SE mode
1 0 2N + 1 1 x PBTL Parallelled BTL configuration. Connect INPUT_C and INPUT_D to GND.
1 1 1N +1 4 x SE Single ended output configuration