ホーム パワー・マネージメント パワー・スイッチ eFuse とホット・スワップ・コントローラ

TPS2330

アクティブ

アクティブ・ローのイネーブル搭載、3V ~ 13V、ホット・スワップ・コントローラ

製品詳細

FET External Vin (min) (V) 3 Vin (max) (V) 13 Vabsmax_cont (V) 15 Current limit (min) (A) 0.01 Current limit (max) (A) 500 Overcurrent response Circuit breaker Fault response Latch-off Soft start Adjustable Features Fault output, Power good signal Rating Catalog Device type eFuses and hot swap controllers Operating temperature range (°C) -40 to 85 Function Inrush current control, Power good signal
FET External Vin (min) (V) 3 Vin (max) (V) 13 Vabsmax_cont (V) 15 Current limit (min) (A) 0.01 Current limit (max) (A) 500 Overcurrent response Circuit breaker Fault response Latch-off Soft start Adjustable Features Fault output, Power good signal Rating Catalog Device type eFuses and hot swap controllers Operating temperature range (°C) -40 to 85 Function Inrush current control, Power good signal
SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Single-Channel High-Side MOSFET Driver
  • Input Voltage: 3 V to 13 V
  • Output dV/dt Control Limits Inrush Current
  • Circuit-Breaker With Programmable Overcurrent
    Threshold and Transient Timer
  • Power-Good Reporting With Transient Filter
  • CMOS- and TTL-Compatible Enable Input
  • Low 5-µA Standby Supply Current (Max)
  • Available in 14-Pin SOIC and TSSOP Package
  • –40°C to 85°C Ambient Temperature Range
  • Electrostatic Discharge Protection
  • Single-Channel High-Side MOSFET Driver
  • Input Voltage: 3 V to 13 V
  • Output dV/dt Control Limits Inrush Current
  • Circuit-Breaker With Programmable Overcurrent
    Threshold and Transient Timer
  • Power-Good Reporting With Transient Filter
  • CMOS- and TTL-Compatible Enable Input
  • Low 5-µA Standby Supply Current (Max)
  • Available in 14-Pin SOIC and TSSOP Package
  • –40°C to 85°C Ambient Temperature Range
  • Electrostatic Discharge Protection

The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush-current control, output-power status reporting, and the ability to discriminate between load transients and faults, are critical requirements for hot-swap applications.

The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pump controls both the rise times and fall times (dV/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period.

DISCH – DISCH should be connected to the source of the external N-channel MOSFET transistor connected to GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as reference-voltage connection for internal gate-voltage-clamp circuitry.

ENABLE or ENABLE –  ENABLE for TPS2330 is active-low. ENABLE for TPS2331 is active-high. When the controller is enabled, GATE voltage powers up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 µs, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than 5 µA.

FAULT  –  FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low. In order to turn the device back on, either the enable pin must be toggled or the input power must be cycled.

GATE – GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled, internal charge-pump circuitry pulls this pin up by sourcing approximately 15 µA. The turnon slew rates depend on the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced by connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up. The charge-pump circuitry generates gate-to-source voltages of 9 V–12 V across the external MOSFET transistor.

IN – IN should be connected to the power source driving the external N-channel MOSFET transistor connected to GATE. The TPS2330/31 draws its operating current from IN, and remains disabled until the IN power supply has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.

ISENSE, ISET – ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the magnitude of the current that generates an overcurrent fault, through an external resistor connected to ISET. An internal current source draws 50 µA from ISET. With a sense resistor from IN to ISENSE, which is also connected to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE is pulled below ISET. To ensure proper circuit breaker operation, VI(ISENSE) and VI(ISET) should never exceed VI(IN).

PWRGD – PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain output and is pulled low during an undervoltage condition. To minimize erroneous PWRGD responses from transients on the voltage rail, the voltage sense circuit incorporates a 20-µs deglitch filter. When VSENSE is lower than the reference voltage (about 1.23 V), PWRGD is active-low to indicate an undervoltage condition on the power-rail voltage. PWRGD may not correctly report power conditions when the device is disabled because there is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD is floating. Therefore, PWRGD is pulled up to its pullup power supply rail in disable mode.

TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering.

VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-µF ceramic capacitor should be connected between VREG and ground to aid in noise rejection. In this configuration, on disabling the device, the internal low-dropout regulator also is disabled, which removes power from the internal circuitry and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V, VREG and IN1 may be connected together. However, under these conditions, disabling the device may not place the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed, thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-µF ceramic capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 µF to 10 µF.

VSENSE – VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses a voltage below approximately 1.23 V, PWRGD is pulled low.

The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush-current control, output-power status reporting, and the ability to discriminate between load transients and faults, are critical requirements for hot-swap applications.

The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pump controls both the rise times and fall times (dV/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period.

DISCH – DISCH should be connected to the source of the external N-channel MOSFET transistor connected to GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as reference-voltage connection for internal gate-voltage-clamp circuitry.

ENABLE or ENABLE –  ENABLE for TPS2330 is active-low. ENABLE for TPS2331 is active-high. When the controller is enabled, GATE voltage powers up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 µs, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than 5 µA.

FAULT  –  FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low. In order to turn the device back on, either the enable pin must be toggled or the input power must be cycled.

GATE – GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled, internal charge-pump circuitry pulls this pin up by sourcing approximately 15 µA. The turnon slew rates depend on the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced by connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up. The charge-pump circuitry generates gate-to-source voltages of 9 V–12 V across the external MOSFET transistor.

IN – IN should be connected to the power source driving the external N-channel MOSFET transistor connected to GATE. The TPS2330/31 draws its operating current from IN, and remains disabled until the IN power supply has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.

ISENSE, ISET – ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the magnitude of the current that generates an overcurrent fault, through an external resistor connected to ISET. An internal current source draws 50 µA from ISET. With a sense resistor from IN to ISENSE, which is also connected to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE is pulled below ISET. To ensure proper circuit breaker operation, VI(ISENSE) and VI(ISET) should never exceed VI(IN).

PWRGD – PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain output and is pulled low during an undervoltage condition. To minimize erroneous PWRGD responses from transients on the voltage rail, the voltage sense circuit incorporates a 20-µs deglitch filter. When VSENSE is lower than the reference voltage (about 1.23 V), PWRGD is active-low to indicate an undervoltage condition on the power-rail voltage. PWRGD may not correctly report power conditions when the device is disabled because there is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD is floating. Therefore, PWRGD is pulled up to its pullup power supply rail in disable mode.

TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering.

VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-µF ceramic capacitor should be connected between VREG and ground to aid in noise rejection. In this configuration, on disabling the device, the internal low-dropout regulator also is disabled, which removes power from the internal circuitry and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V, VREG and IN1 may be connected together. However, under these conditions, disabling the device may not place the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed, thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-µF ceramic capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 µF to 10 µF.

VSENSE – VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses a voltage below approximately 1.23 V, PWRGD is pulled low.

ダウンロード 字幕付きのビデオを表示 ビデオ

技術資料

star =TI が選定したこの製品の主要ドキュメント
結果が見つかりませんでした。検索条件をクリアしてから、再度検索を試してください。
6 をすべて表示
種類 タイトル 最新の英語版をダウンロード 日付
* データシート Single Hot-Swap Power Controllers with Circuit Breaker and Power Good Reporting データシート (Rev. G) 2013年 5月 10日
ユーザー・ガイド TPS5102 Buck Controller Evaluation Module User's Guide (Rev. A) PDF | HTML 2022年 3月 14日
セレクション・ガイド 電源 IC セレクション・ガイド 2018 (Rev. R 翻訳版) 英語版 (Rev.R) 2018年 9月 13日
セレクション・ガイド Hot Swap Selection Tool 2015年 7月 28日
ユーザー・ガイド 48-V Telecom Hot-Swap Evaluation Module and Interface Card 2001年 3月 1日
ユーザー・ガイド Dual Hot Swap Controller Evaluation Module and Interface Card 2000年 4月 10日

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

計算ツール

TPS23XXCALC TPS230x/1x/2x/3x Design Calculator

This design utility allows the user to calculate the component values for external MOSFET, current limit setting, current limit sense resistor RSENSE, current limit setting resistor RSET, GATE capacitance Cg, TIMER capacitance CT, power-good feedback resistor divider, and other essential components (...)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

製品
eFuse とホット・スワップ・コントローラ
TPS2300 個別チャネル・サーキット・ブレーカとアクティブ・ローのイネーブル搭載、3V ~ 13V、デュアル・チャネル・ホット・スワップ TPS2301 個別チャネル・サーキット・ブレーカとパワー・グッド搭載、3V ~ 13V、デュアル・チャネル・ホット・スワップ TPS2310 相互依存チャネル・サーキット・ブレーカとアクティブ・ローのイネーブル搭載、3V ~ 13V、デュアル・チャネル・ホット・スワップ TPS2311 相互依存チャネル・サーキット・ブレーカとパワー・グッド搭載、3V ~ 13V、デュアル・チャネル・ホット・スワップ TPS2320 アクティブ・ローのイネーブル搭載、3V ~ 13V、デュアル・チャネル・ホット・スワップ TPS2321 アクティブ・ハイのイネーブル搭載、3V ~ 13V、デュアル・チャネル・ホット・スワップ TPS2330 アクティブ・ローのイネーブル搭載、3V ~ 13V、ホット・スワップ・コントローラ TPS2331 アクティブ・ハイのイネーブル搭載、3V ~ 13V、ホット・スワップ・コントローラ
計算ツール

TVS-RECOMMENDATION-CALC TVS diode recommendation tool

This tool suggests suitable TVS for given system parameters and abs max voltage rating of the device.
サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

こちらの設計リソースは、このカテゴリに属する製品の大半をサポートしています。

サポート状況を確認するには、製品の詳細ページをご覧ください。

シミュレーション・ツール

PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®

PSpice® for TI は、各種アナログ回路の機能評価に役立つ、設計とシミュレーション向けの環境です。設計とシミュレーションに適したこのフル機能スイートは、Cadence® のアナログ分析エンジンを使用しています。PSpice for TI は無償で使用でき、アナログや電源に関する TI の製品ラインアップを対象とする、業界でも有数の大規模なモデル・ライブラリが付属しているほか、選択された一部のアナログ動作モデルも利用できます。

設計とシミュレーション向けの環境である PSpice for TI (...)
パッケージ ピン数 ダウンロード
SOIC (D) 14 オプションの表示
TSSOP (PW) 14 オプションの表示

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 材質成分
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

サポートとトレーニング

TI E2E™ フォーラムでは、TI のエンジニアからの技術サポートを提供

コンテンツは、TI 投稿者やコミュニティ投稿者によって「現状のまま」提供されるもので、TI による仕様の追加を意図するものではありません。使用条件をご確認ください。

TI 製品の品質、パッケージ、ご注文に関するお問い合わせは、TI サポートをご覧ください。​​​​​​​​​​​​​​

ビデオ