SLVS947C October   2009  – August 2014 TPS53125

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematics
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  PWM Operation
      2. 8.3.2  Drivers
      3. 8.3.3  PWM Frequency and Adaptive On-Time Control
      4. 8.3.4  5-Volt Regulator
      5. 8.3.5  Soft Start
      6. 8.3.6  Pre-Bias Support
      7. 8.3.7  Output Discharge Control
      8. 8.3.8  Over Current Limit
      9. 8.3.9  Over/Under Voltage Protection
      10. 8.3.10 UVLO Protection
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements (QFN)
      2. 9.2.2 Detailed Design Procedure (QFN)
        1. 9.2.2.1 Choose Inductor
        2. 9.2.2.2 Choose Output Capacitor
        3. 9.2.2.3 Choose Input Capacitor
        4. 9.2.2.4 Choose Bootstrap Capacitor
        5. 9.2.2.5 Choose VREG5 and V5FILT Capacitor
        6. 9.2.2.6 Choose Output Voltage Set Point Resistors
        7. 9.2.2.7 Choose Over Current Set Point Resistor
        8. 9.2.2.8 Choose Soft Start Capacitor
      3. 9.2.3 Application Curves (QFN)
    3. 9.3 Typical Application Circuit, TSSOP
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Suggestions
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ

1 Features

  • D-CAP2™ Mode Control
    • Fast Transient Response
    • No External Parts Required for Loop Compensation
    • Compatible With Ceramic Output Capacitors
  • High Initial Reference Accuracy (±1%)
  • Low Output Ripple
  • Wide Input Voltage Range: 4.5 V to 24 V
  • Output Voltage Range: 0.76 V to 5.5 V
  • Low-Side RDS(ON) Loss-Less Current Sensing
  • Adaptive Gate Drivers with Integrated Boost Diode
  • Adjustable Soft Start
  • Non-Sinking Pre-Biased Soft Start
  • 350-kHz Switching Frequency
  • Cycle-by-Cycle Over-Current Limiting Control
  • 30-mV to 300-mV OCP Threshold Voltage
  • Thermally Compensated OCP by 4000 ppm/°C at ITRIP

2 Applications

  • Point-of-Load Regulation in Low Power Systems for Wide Range of Applications
    • Digital TV Power Supply
    • Networking Home Terminal
    • Digital Set-Top Box (STB)
    • DVD Player/Recorder
    • Gaming Consoles

3 Description

The TPS53125 is a dual, adaptive on-time D-CAP2™ mode synchronous buck controller. The part enables system designers to cost effectively complete the suite of various end equipment's power bus regulators with a low external component count and low standby consumption. The main control loop for the TPS53125 uses the D-CAP™ Mode topology which provides a very fast transient response with no external component.

The TPS53125 also has a proprietary circuit that enables the device to adapt not only low equivalent series resistance (ESR) output capacitors such as POSCAP/SP-CAP, but also ceramic capacitor. The part provides a convenient and efficient operation with conversion voltages from 4.5 V to 24 V and output voltage from 0.76 V to 5.5 V.

The TPS53125 is available in 24-pin RGE and PW packages, and is specified from –40°C to 85°C ambient temperature range.

Device Information(1)

DEVICE NAME PACKAGE BODY SIZE
TPS53125 VQFN (24) 4 mm x 4 mm
TSSOP (24) 4.4 mm x 7.8 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematics

TPS53125 typapp_QFN_lvs947.gif
TPS53125 typapp_TSSOP_lvs947.gif